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[/] [mblite/] [trunk/] [designs/] [core_syn/] [README] - Blame information for rev 7

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Design: core
Description: The memory organization is as follows
core
|
`- imem
|
`- dmem
 
The dmem output is tied to the testbench for debugging
purposes.
 
The memory is preloaded with the hello world program
 
- MAKE SURE THE SIMULATOR IS SET TO TIME RESOLUTION OF 1 PS
- REPLACE mblite_soc_*.vhd WITH THE GENERATED VHDL NETLIST
- OPTIONALLY LOAD THE STANDARD DELAY FORMAT FILE IN MODELSIM
- THE TOOL mblite/sw/util/bin2rom CAN BE USED TO GENERATE
  THE INTIALIZATION ASSIGNMENT FROM A BINARY FORMAT

Line No.	Rev	Author	Line
1	2	takar	`Design: core`
2			`Description: The memory organization is as follows`
3			`core`
4			`\|`
5			`- imem
6			`\|`
7			`- dmem
8
9			`The dmem output is tied to the testbench for debugging`
10			`purposes.`
11
12			`The memory is preloaded with the hello world program`
13
14			`- MAKE SURE THE SIMULATOR IS SET TO TIME RESOLUTION OF 1 PS`
15			`- REPLACE mblite_soc_*.vhd WITH THE GENERATED VHDL NETLIST`
16			`- OPTIONALLY LOAD THE STANDARD DELAY FORMAT FILE IN MODELSIM`
17			`- THE TOOL mblite/sw/util/bin2rom CAN BE USED TO GENERATE`
18			`THE INTIALIZATION ASSIGNMENT FROM A BINARY FORMAT`

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Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_syn/] [README] - Blame information for rev 7