OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_wb/] [testbench.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
2
--
3
--      Input file         : config_Pkg.vhd
4
--      Design name        : config_Pkg
5
--      Author             : Tamar Kranenburg
6
--      Company            : Delft University of Technology
7
--                         : Faculty EEMCS, Department ME&CE
8
--                         : Systems and Circuits group
9
--
10
--      Description        : Testbench instantiates core, data memory, instruction memory
11
--                           and a character device.
12
--
13
----------------------------------------------------------------------------------------------
14
 
15 8 takar
library ieee;
16
use ieee.std_logic_1164.all;
17
use ieee.std_logic_unsigned.all;
18 2 takar
 
19 8 takar
library mblite;
20
use mblite.config_Pkg.all;
21
use mblite.core_Pkg.all;
22
use mblite.std_Pkg.all;
23 2 takar
 
24
use std.textio.all;
25
 
26 8 takar
entity testbench is
27
end testbench;
28 2 takar
 
29 8 takar
architecture arch of testbench is
30 2 takar
 
31 8 takar
    signal imem_o : imem_out_type;
32
    signal imem_i : imem_in_type;
33 2 takar
 
34 8 takar
    signal wb_o : wb_mst_out_type;
35
    signal wb_i : wb_mst_in_type;
36 2 takar
 
37 8 takar
    signal sys_clk_i : std_logic := '0';
38
    signal sys_int_i : std_logic;
39
    signal sys_rst_i : std_logic;
40 2 takar
 
41 8 takar
    constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
42
    signal std_out_ack : std_logic;
43 2 takar
 
44 8 takar
    signal stdo_ena : std_logic;
45 2 takar
 
46 8 takar
    signal dmem_ena : std_logic;
47
    signal dmem_dat : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
48
    signal dmem_sel : std_logic_vector(3 downto 0);
49 2 takar
 
50 8 takar
    constant rom_size : integer := 16;
51
    constant ram_size : integer := 16;
52 2 takar
 
53 8 takar
begin
54 2 takar
 
55 8 takar
    sys_clk_i <= not sys_clk_i after 10000 ps;
56
    sys_rst_i <= '1' after 0 ps, '0' after  150000 ps;
57
    sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
58 2 takar
 
59 8 takar
    timeout: process(sys_clk_i)
60
    begin
61
        if NOW = 10 ms then
62
            report "TIMEOUT" severity FAILURE;
63
        end if;
64 2 takar
 
65
        -- BREAK ON EXIT (0xB8000000)
66 8 takar
        if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
67 2 takar
            -- Make sure the simulator finishes when an error is encountered.
68
            -- For modelsim: see menu Simulate -> Runtime options -> Assertions
69 8 takar
            report "FINISHED" severity FAILURE;
70
        end if;
71
    end process;
72 2 takar
 
73
    -- Character device
74 8 takar
    wb_stdio_slave: process(sys_clk_i)
75
        variable s    : line;
76
        variable byte : std_logic_vector(7 downto 0);
77
        variable char : character;
78
    begin
79
        if rising_edge(sys_clk_i) then
80
            if (wb_o.stb_o and wb_o.cyc_o and compare(wb_o.adr_o, std_out_adr)) = '1' then
81
                if wb_o.we_o = '1' and std_out_ack = '0' then
82 2 takar
                -- WRITE STDOUT
83
                    std_out_ack <= '1';
84 8 takar
                    case wb_o.sel_o is
85
                        when "0001" => byte := wb_o.dat_o( 7 downto  0);
86
                        when "0010" => byte := wb_o.dat_o(15 downto  8);
87
                        when "0100" => byte := wb_o.dat_o(23 downto 16);
88
                        when "1000" => byte := wb_o.dat_o(31 downto 24);
89
                        when others => null;
90
                    end case;
91 2 takar
                    char := character'val(my_conv_integer(byte));
92 8 takar
                    if byte = X"0D" then
93 2 takar
                        -- Ignore character 13
94 8 takar
                    elsif byte = X"0A" then
95 2 takar
                        -- Writeline on character 10 (newline)
96
                        writeline(output, s);
97 8 takar
                    else
98 2 takar
                        -- Write to buffer
99
                        write(s, char);
100 8 takar
                    end if;
101
                elsif std_out_ack = '0' then
102 2 takar
                    std_out_ack <= '1';
103 8 takar
                end if;
104
            else
105 2 takar
                std_out_ack <= '0';
106 8 takar
            end if;
107
        end if;
108 2 takar
 
109 8 takar
    end process;
110 2 takar
 
111
    wb_i.clk_i <= sys_clk_i;
112
    wb_i.rst_i <= sys_rst_i;
113
    wb_i.int_i <= sys_int_i;
114
 
115 8 takar
    dmem_ena <= wb_o.stb_o and wb_o.cyc_o and not compare(wb_o.adr_o, std_out_adr);
116 2 takar
 
117 8 takar
    process(wb_o.stb_o, wb_o.cyc_o, std_out_ack, wb_o.adr_o)
118
    begin
119
        if not compare(wb_o.adr_o, std_out_adr) = '1' then
120
            wb_i.ack_i <= wb_o.stb_o and wb_o.cyc_o after 2 ns;
121
        else
122
            wb_i.ack_i <= std_out_ack after 22 ns;
123
        end if;
124
    end process;
125 2 takar
 
126 8 takar
    imem : sram generic map
127 2 takar
    (
128
        WIDTH => CFG_IMEM_WIDTH,
129
        SIZE => rom_size - 2
130
    )
131 8 takar
    port map
132 2 takar
    (
133
        dat_o => imem_i.dat_i,
134
        dat_i => "00000000000000000000000000000000",
135 8 takar
        adr_i => imem_o.adr_o(rom_size - 1 downto 2),
136 2 takar
        wre_i => '0',
137
        ena_i => imem_o.ena_o,
138
        clk_i => sys_clk_i
139
    );
140
 
141 8 takar
    dmem_sel <= wb_o.sel_o when wb_o.we_o = '1' else (others => '0');
142
    wb_i.dat_i <= X"61616161" when std_out_ack = '1' else dmem_dat;
143 2 takar
 
144 8 takar
    dmem : sram_4en generic map
145 2 takar
    (
146
        WIDTH => CFG_DMEM_WIDTH,
147
        SIZE => ram_size - 2
148
    )
149 8 takar
    port map
150 2 takar
    (
151
        dat_o => dmem_dat,
152
        dat_i => wb_o.dat_o,
153 8 takar
        adr_i => wb_o.adr_o(ram_size - 1 downto 2),
154 2 takar
        wre_i => dmem_sel,
155
        ena_i => dmem_ena,
156
        clk_i => sys_clk_i
157
    );
158
 
159 8 takar
    core_wb0 : core_wb port map
160 2 takar
    (
161
        imem_o => imem_o,
162
        wb_o   => wb_o,
163
        imem_i => imem_i,
164
        wb_i   => wb_i
165
    );
166
 
167 8 takar
end arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.