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[/] [mblite/] [trunk/] [hw/] [core/] [core_wb_adapter.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
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--
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--      Input file         : core_wb_adapter.vhd
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--      Design name        : core_wb_adapter.vhd
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Wishbone adapter for the MB-Lite microprocessor. The data output
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--                           is registered for multicycle transfers. This adapter implements
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--                           the synchronous Wishbone Bus protocol, Rev3B.
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--
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY mblite;
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USE mblite.config_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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ENTITY core_wb_adapter IS PORT
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(
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    dmem_i : OUT dmem_in_type;
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    wb_o   : OUT wb_mst_out_type;
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    dmem_o : IN dmem_out_type;
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    wb_i   : IN wb_mst_in_type
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);
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END core_wb_adapter;
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ARCHITECTURE arch OF core_wb_adapter IS
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    SIGNAL r_cyc_o : std_ulogic;
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    SIGNAL rin_cyc_o : std_ulogic;
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    SIGNAL r_data, rin_data : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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    SIGNAL s_wait : std_ulogic;
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BEGIN
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    -- Direct input-output connections
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    wb_o.adr_o   <= dmem_o.adr_o;
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    wb_o.sel_o   <= dmem_o.sel_o;
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    wb_o.we_o    <= dmem_o.we_o;
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    dmem_i.dat_i <= wb_i.dat_i;
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    -- synchronous bus control connections
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    wb_o.cyc_o <= r_cyc_o OR wb_i.ack_i;
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    wb_o.stb_o <= r_cyc_o;
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    -- asynchronous core enable connection
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    dmem_i.ena_i <= '0' WHEN (dmem_o.ena_o = '1' AND rin_cyc_o = '1') OR s_wait = '1' ELSE '1';
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    wb_o.dat_o   <= rin_data;
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    -- logic for wishbone master
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    wb_adapter_comb: PROCESS(wb_i, dmem_o, r_cyc_o, r_data)
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    BEGIN
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        IF wb_i.rst_i = '1' THEN
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            -- reset bus
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            rin_data <= r_data;
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            rin_cyc_o <= '0';
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            s_wait <= '0';
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        ELSIF r_cyc_o = '1' AND wb_i.ack_i = '1' THEN
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            -- terminate wishbone cycle
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            rin_data <= r_data;
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            rin_cyc_o <= '0';
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            s_wait <= '0';
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        ELSIF dmem_o.ena_o = '1' AND wb_i.ack_i = '1' THEN
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            -- wishbone bus is occuppied
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            rin_data <= r_data;
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            rin_cyc_o <= '1';
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            s_wait <= '1';
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        ELSIF r_cyc_o = '0' AND dmem_o.ena_o = '1' AND wb_i.ack_i = '0' THEN
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            -- start wishbone cycle
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            rin_data <= dmem_o.dat_o;
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            rin_cyc_o <= '1';
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            s_wait <= '0';
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        ELSE
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            -- maintain wishbone cycle
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            rin_data <= r_data;
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            rin_cyc_o <= r_cyc_o;
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            s_wait <= '0';
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        END IF;
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    END PROCESS;
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    wb_adapter_seq: PROCESS(wb_i.clk_i)
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    BEGIN
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        IF rising_edge(wb_i.clk_i) THEN
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            r_cyc_o <= rin_cyc_o;
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            r_data <= rin_data;
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        END IF;
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    END PROCESS;
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END arch;

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