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[/] [mblite/] [trunk/] [hw/] [std/] [dsram.vhd] - Blame information for rev 7

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Line No. Rev Author Line
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----------------------------------------------------------------------------------------------
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--
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--      Input file         : dsram.vhd
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--      Design name        : dsram
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
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--                           Write Port.
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--
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--
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY mblite;
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USE mblite.std_Pkg.ALL;
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ENTITY dsram IS GENERIC
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(
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    WIDTH : positive := 32;
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    SIZE  : positive := 8
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);
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PORT
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(
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    dat_o   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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    adr_i   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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    ena_i   : IN std_logic;
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    dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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    adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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    wre_i   : IN std_logic;
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    clk_i   : IN std_logic
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);
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END dsram;
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ARCHITECTURE arch OF dsram IS
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    TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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    SIGNAL ram :  ram_type;
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BEGIN
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    PROCESS(clk_i)
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    BEGIN
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        IF rising_edge(clk_i) THEN
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            IF ena_i = '1' THEN
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                IF wre_i = '1' THEN
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                    ram(my_conv_integer(adr_w_i)) <= dat_w_i;
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                END IF;
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                dat_o <= ram(my_conv_integer(adr_i));
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            END IF;
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        END IF;
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    END PROCESS;
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END arch;

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