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[/] [mblite/] [trunk/] [hw/] [std/] [std_Pkg.vhd] - Blame information for rev 10

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----------------------------------------------------------------------------------------------
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--
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--      Input file         : std_Pkg.vhd
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--      Design name        : std_Pkg
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Package with several standard components.
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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PACKAGE std_Pkg IS
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----------------------------------------------------------------------------------------------
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-- STANDARD COMPONENTS IN STD_PKG
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----------------------------------------------------------------------------------------------
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    component sram generic
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    port
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    (
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        dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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        dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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        adr_i : in std_logic_vector(SIZE - 1 downto 0);
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        wre_i : in std_logic;
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        ena_i : in std_logic;
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        clk_i : in std_logic
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    );
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    end component;
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    component sram_4en generic
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    port
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    (
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        dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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        dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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        adr_i : in std_logic_vector(SIZE - 1 downto 0);
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        wre_i : in std_logic_vector(3 downto 0);
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        ena_i : in std_logic;
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        clk_i : in std_logic
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    );
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    end component;
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    component dsram generic
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    port
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    (
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        dat_o   : out std_logic_vector(WIDTH - 1 downto 0);
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        adr_i   : in std_logic_vector(SIZE - 1 downto 0);
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        ena_i   : in std_logic;
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        dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
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        adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
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        wre_i   : in std_logic;
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        clk_i   : in std_logic
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    );
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    end component;
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----------------------------------------------------------------------------------------------
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-- FUNCTIONS IN STD_PKG
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----------------------------------------------------------------------------------------------
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    function v_or(d : std_logic_vector) return std_logic;
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    function is_zero(d : std_logic_vector) return std_logic;
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    function is_not_zero(d : std_logic_vector) return std_logic;
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    function my_conv_integer(a: std_logic_vector) return integer;
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    function notx(d : std_logic_vector) return boolean;
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    function compare(a, b : std_logic_vector) return std_logic;
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    function multiply(a, b : std_logic_vector) return std_logic_vector;
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    function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
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    function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
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    function increment(a : std_logic_vector) return std_logic_vector;
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    function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
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    function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
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    function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
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end std_Pkg;
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PACKAGE BODY std_Pkg IS
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-- Unary OR reduction
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    function v_or(d : std_logic_vector) return std_logic is
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        variable z : std_logic;
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    begin
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        z := '0';
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        if notx (d) then
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            for i in d'range loop
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                z := z or d(i);
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            end loop;
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        end if;
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        return z;
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    end;
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-- Check for ones in the vector
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    function is_not_zero(d : std_logic_vector) return std_logic is
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        variable z : std_logic_vector(d'range);
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    begin
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        z := (others => '0');
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        if notx(d) then
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            if d = z then
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                return '0';
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            else
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                return '1';
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            end if;
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        else
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            return '0';
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        end if;
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    end;
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-- Check for ones in the vector
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    function is_zero(d : std_logic_vector) return std_logic is
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    begin
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        return not is_not_zero(d);
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    end;
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    -- rewrite conv_integer to avoid modelsim warnings
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    function my_conv_integer(a : std_logic_vector) return integer is
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        variable res : integer range 0 to 2**a'length-1;
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    begin
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        res := 0;
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        if (notx(a)) then
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            res := to_integer(unsigned(a));
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        end if;
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        return res;
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    end;
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    function compare(a, b : std_logic_vector) return std_logic is
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        variable z : std_logic;
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    begin
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        if notx(a & b) and a = b then
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            return '1';
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        else
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            return '0';
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        end if;
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    end;
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-- Unary NOT X test
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    function notx(d : std_logic_vector) return boolean is
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        variable res : boolean;
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    begin
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        res := true;
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-- pragma translate_off
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        res := not is_x(d);
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-- pragma translate_on
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        return (res);
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    end;
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-- -- 32 bit shifter
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-- -- SYNOPSIS:
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-- --    value: value to be shifted
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-- --    shamt: shift amount
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-- --    s 0 / 1: shift right / left
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-- --    t 0 / 1: shift logical / arithmetic
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-- -- PSEUDOCODE (from microblaze reference guide)
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-- --     if S = 1 then
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-- --          (rD) = (rA) << (rB)[27:31]
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-- --     else
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-- --      if T = 1 then
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-- --         if ((rB)[27:31]) != 0 then
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-- --              (rD)[0:(rB)[27:31]-1] = (rA)[0]
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-- --              (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
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-- --         else
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-- --              (rD) = (rA)
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-- --      else
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-- --         (rD) = (rA) >> (rB)[27:31]
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    function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
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    begin
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        if s = '1' then
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            -- left arithmetic or logical shift
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            return shift_left(value, shamt);
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        else
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            if t = '1' then
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                -- right arithmetic shift
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                return shift_right(value, shamt, value(31));
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            else
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                -- right logical shift
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                return shift_right(value, shamt, '0');
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            end if;
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        end if;
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    end;
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    function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
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        variable result: std_logic_vector(31 downto 0);
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        variable paddings: std_logic_vector(15 downto 0);
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    begin
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        paddings := (others => '0');
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        result := value;
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        if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
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        if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
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        if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
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        if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
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        if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 );         end if;
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        return result;
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    end;
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    function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
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        variable result: std_logic_vector(31 downto 0);
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        variable paddings: std_logic_vector(15 downto 0);
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    begin
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        paddings := (others => padding);
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        result := value;
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        if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
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        if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto  8); end if;
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        if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto  4); end if;
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        if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto  2); end if;
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        if (shamt(0) = '1') then result := paddings( 0 )         & result(31 downto  1); end if;
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        return result;
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    end;
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    function multiply(a, b: std_logic_vector) return std_logic_vector is
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        variable x: std_logic_vector (a'length + b'length - 1 downto 0);
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    begin
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        x := std_logic_vector(signed(a) * signed(b));
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        return x(31 downto 0);
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    end;
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    function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
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        variable a: std_logic_vector (size - 1 downto 0);
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    begin
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        a(size - 1 downto value'length) := (others => fill);
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        a(value'length - 1 downto 0) := value;
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        return a;
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    end;
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    function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
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        variable x : std_logic_vector(a'length + 1 downto 0);
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    begin
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        x := (others => '0');
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        if notx (a & b & ci) then
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            x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
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        end if;
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        return x(a'length + 1 downto 1);
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    end;
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    function increment(a : std_logic_vector) return std_logic_vector is
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        variable x : std_logic_vector(a'length-1 downto 0);
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    begin
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        x := (others => '0');
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        if notx (a) then
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            x := std_logic_vector(signed(a) + 1);
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        end if;
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        return x;
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    end;
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end std_Pkg;

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