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[/] [mblite/] [trunk/] [hw/] [std/] [std_Pkg.vhd] - Blame information for rev 5

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1 2 takar
----------------------------------------------------------------------------------------------
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--
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--      Input file         : std_Pkg.vhd
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--      Design name        : std_Pkg
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Package with several standard components.
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--
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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PACKAGE std_Pkg IS
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----------------------------------------------------------------------------------------------
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-- STANDARD COMPONENTS IN STD_PKG
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----------------------------------------------------------------------------------------------
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    COMPONENT sram GENERIC
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    PORT
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    (
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        dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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        wre_i : IN std_ulogic;
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        ena_i : IN std_ulogic;
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        clk_i : IN std_ulogic
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    );
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    END COMPONENT;
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    COMPONENT sram_4en GENERIC
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    PORT
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    (
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        dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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        wre_i : IN std_ulogic_vector(3 DOWNTO 0);
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        ena_i : IN std_ulogic;
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        clk_i : IN std_ulogic
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    );
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    END COMPONENT;
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    COMPONENT dsram GENERIC
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    (
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        WIDTH : positive;
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        SIZE  : positive
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    );
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    PORT
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    (
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        dat_o   : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        adr_i   : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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        ena_i   : IN std_ulogic;
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        dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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        adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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        wre_i   : IN std_ulogic;
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        clk_i   : IN std_ulogic
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    );
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    END COMPONENT;
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----------------------------------------------------------------------------------------------
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-- FUNCTIONS IN STD_PKG
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----------------------------------------------------------------------------------------------
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    FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
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    FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
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    FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
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    FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
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    FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
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    FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
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    FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
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    FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
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    FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
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    FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
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    FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
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    FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
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    FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
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END std_Pkg;
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PACKAGE BODY std_Pkg IS
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-- Unary OR reduction
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    FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
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        VARIABLE z : std_ulogic;
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    BEGIN
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        z := '0';
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        IF notx (d) THEN
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            FOR i IN d'range LOOP
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                z := z OR d(i);
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            END LOOP;
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        END IF;
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        RETURN z;
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    END;
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-- Check for ones in the vector
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    FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
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        VARIABLE z : std_ulogic_vector(d'range);
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    BEGIN
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        z := (OTHERS => '0');
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        IF notx(d) THEN
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            IF d = z THEN
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                RETURN '0';
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            ELSE
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                RETURN '1';
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            END IF;
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        ELSE
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            RETURN '0';
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        END IF;
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    END;
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-- Check for ones in the vector
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    FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
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    BEGIN
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        RETURN NOT is_not_zero(d);
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    END;
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    -- rewrite conv_integer to avoid modelsim warnings
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    FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
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        VARIABLE res : integer RANGE 0 TO 2**a'length-1;
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    BEGIN
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        res := 0;
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        IF (notx(a)) THEN
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            res := to_integer(unsigned(a));
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        END IF;
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        RETURN res;
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    END;
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    FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
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        VARIABLE z : std_ulogic;
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    BEGIN
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        IF notx(a & b) AND a = b THEN
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            RETURN '1';
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        ELSE
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            RETURN '0';
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        END IF;
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    END;
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-- Unary NOT X test
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    FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
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        VARIABLE res : boolean;
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    BEGIN
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        res := true;
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-- pragma translate_off
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        res := NOT is_x(d);
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-- pragma translate_on
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        RETURN (res);
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    END;
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-- -- 32 bit shifter
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-- -- SYNOPSIS:
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-- --    value: value to be shifted
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-- --    shamt: shift amount
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-- --    s 0 / 1: shift right / left
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-- --    t 0 / 1: shift logical / arithmetic
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-- -- PSEUDOCODE (from microblaze reference guide)
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-- --     if S = 1 then
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-- --          (rD) ← (rA) << (rB)[27:31]
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-- --     else
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-- --      if T = 1 then
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-- --         if ((rB)[27:31]) ≠ 0 then
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-- --              (rD)[0:(rB)[27:31]-1] ← (rA)[0]
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-- --              (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
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-- --         else
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-- --              (rD) ← (rA)
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-- --      else
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-- --         (rD) ← (rA) >> (rB)[27:31]
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    FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
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    BEGIN
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        IF s = '1' THEN
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            -- left arithmetic or logical shift
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            RETURN shift_left(value, shamt);
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        ELSE
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            IF t = '1' THEN
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                -- right arithmetic shift
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                RETURN shift_right(value, shamt, value(31));
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            ELSE
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                -- right logical shift
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                RETURN shift_right(value, shamt, '0');
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            END IF;
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        END IF;
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    END;
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    FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
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        VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
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        VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
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    BEGIN
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        paddings := (OTHERS => '0');
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        result := value;
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        IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
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        IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
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        IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
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        IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
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        IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 );         END IF;
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        RETURN result;
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    END;
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    FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
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        VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
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        VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
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    BEGIN
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        paddings := (OTHERS => padding);
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        result := value;
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        IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
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        IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO  8); END IF;
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        IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO  4); END IF;
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        IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO  2); END IF;
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        IF (shamt(0) = '1') THEN result := paddings( 0 )         & result(31 DOWNTO  1); END IF;
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        RETURN result;
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    END;
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    FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
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        VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
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    BEGIN
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        x := std_ulogic_vector(signed(a) * signed(b));
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        RETURN x(31 DOWNTO 0);
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    END;
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    FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
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        VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
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    BEGIN
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        a(size - 1 DOWNTO value'length) := (OTHERS => fill);
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        a(value'length - 1 DOWNTO 0) := value;
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        return a;
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    END;
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    FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
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        VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
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    BEGIN
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        x := (OTHERS => '0');
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        IF notx (a & b & ci) THEN
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            x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
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        END IF;
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        RETURN x(a'length + 1 DOWNTO 1);
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    END;
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    FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
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        VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
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    BEGIN
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        x := (OTHERS => '0');
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        IF notx (a) THEN
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            x := std_ulogic_vector(signed(a) + 1);
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        END IF;
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        RETURN x;
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    END;
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END std_Pkg;

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