OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [hw/] [std/] [std_Pkg.vhd] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
2
--
3
--      Input file         : std_Pkg.vhd
4
--      Design name        : std_Pkg
5
--      Author             : Tamar Kranenburg
6
--      Company            : Delft University of Technology
7
--                         : Faculty EEMCS, Department ME&CE
8
--                         : Systems and Circuits group
9
--
10
--      Description        : Package with several standard components.
11
--
12
----------------------------------------------------------------------------------------------
13
 
14
LIBRARY ieee;
15
USE ieee.std_logic_1164.ALL;
16
USE ieee.numeric_std.ALL;
17
 
18
PACKAGE std_Pkg IS
19
 
20
----------------------------------------------------------------------------------------------
21
-- STANDARD COMPONENTS IN STD_PKG
22
----------------------------------------------------------------------------------------------
23
 
24
    COMPONENT sram GENERIC
25
    (
26
        WIDTH : positive;
27
        SIZE  : positive
28
    );
29
    PORT
30
    (
31 6 takar
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
32
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
33
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
34
        wre_i : IN std_logic;
35
        ena_i : IN std_logic;
36
        clk_i : IN std_logic
37 2 takar
    );
38
    END COMPONENT;
39
 
40
    COMPONENT sram_4en GENERIC
41
    (
42
        WIDTH : positive;
43
        SIZE  : positive
44
    );
45
    PORT
46
    (
47 6 takar
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
48
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
49
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
50
        wre_i : IN std_logic_vector(3 DOWNTO 0);
51
        ena_i : IN std_logic;
52
        clk_i : IN std_logic
53 2 takar
    );
54
    END COMPONENT;
55
 
56
    COMPONENT dsram GENERIC
57
    (
58
        WIDTH : positive;
59
        SIZE  : positive
60
    );
61
    PORT
62
    (
63 6 takar
        dat_o   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
64
        adr_i   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
65
        ena_i   : IN std_logic;
66
        dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
67
        adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
68
        wre_i   : IN std_logic;
69
        clk_i   : IN std_logic
70 2 takar
    );
71
    END COMPONENT;
72
 
73
----------------------------------------------------------------------------------------------
74
-- FUNCTIONS IN STD_PKG
75
----------------------------------------------------------------------------------------------
76
 
77 6 takar
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic;
78
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic;
79
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic;
80
    FUNCTION my_conv_integer(a: std_logic_vector) RETURN integer;
81
    FUNCTION notx(d : std_logic_vector) RETURN boolean;
82
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic;
83
    FUNCTION multiply(a, b : std_logic_vector) RETURN std_logic_vector;
84
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector;
85
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector;
86
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector;
87
    FUNCTION shift(value : std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector;
88
    FUNCTION shift_left(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector;
89
    FUNCTION shift_right(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector;
90 2 takar
 
91
END std_Pkg;
92
 
93
PACKAGE BODY std_Pkg IS
94
 
95
-- Unary OR reduction
96 6 takar
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic IS
97
        VARIABLE z : std_logic;
98 2 takar
    BEGIN
99
        z := '0';
100
        IF notx (d) THEN
101
            FOR i IN d'range LOOP
102
                z := z OR d(i);
103
            END LOOP;
104
        END IF;
105
        RETURN z;
106
    END;
107
 
108
-- Check for ones in the vector
109 6 takar
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic IS
110
        VARIABLE z : std_logic_vector(d'range);
111 2 takar
    BEGIN
112
        z := (OTHERS => '0');
113
        IF notx(d) THEN
114
 
115
            IF d = z THEN
116
                RETURN '0';
117
            ELSE
118
                RETURN '1';
119
            END IF;
120
 
121
        ELSE
122
            RETURN '0';
123
        END IF;
124
    END;
125
 
126
-- Check for ones in the vector
127 6 takar
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic IS
128 2 takar
    BEGIN
129
        RETURN NOT is_not_zero(d);
130
    END;
131
 
132
    -- rewrite conv_integer to avoid modelsim warnings
133 6 takar
    FUNCTION my_conv_integer(a : std_logic_vector) RETURN integer IS
134 2 takar
        VARIABLE res : integer RANGE 0 TO 2**a'length-1;
135
    BEGIN
136
        res := 0;
137
        IF (notx(a)) THEN
138
            res := to_integer(unsigned(a));
139
        END IF;
140
        RETURN res;
141
    END;
142
 
143 6 takar
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic IS
144
        VARIABLE z : std_logic;
145 2 takar
    BEGIN
146
 
147
        IF notx(a & b) AND a = b THEN
148
            RETURN '1';
149
        ELSE
150
            RETURN '0';
151
        END IF;
152
 
153
    END;
154
 
155
-- Unary NOT X test
156 6 takar
    FUNCTION notx(d : std_logic_vector) RETURN boolean IS
157 2 takar
        VARIABLE res : boolean;
158
    BEGIN
159
        res := true;
160
-- pragma translate_off
161
        res := NOT is_x(d);
162
-- pragma translate_on
163
        RETURN (res);
164
    END;
165
 
166
-- -- 32 bit shifter
167
-- -- SYNOPSIS:
168
-- --    value: value to be shifted
169
-- --    shamt: shift amount
170
-- --    s 0 / 1: shift right / left
171
-- --    t 0 / 1: shift logical / arithmetic
172
-- -- PSEUDOCODE (from microblaze reference guide)
173
-- --     if S = 1 then
174
-- --          (rD) ← (rA) << (rB)[27:31]
175
-- --     else
176
-- --      if T = 1 then
177
-- --         if ((rB)[27:31]) ≠ 0 then
178
-- --              (rD)[0:(rB)[27:31]-1] ← (rA)[0]
179
-- --              (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
180
-- --         else
181
-- --              (rD) ← (rA)
182
-- --      else
183
-- --         (rD) ← (rA) >> (rB)[27:31]
184
 
185 6 takar
    FUNCTION shift(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector IS
186 2 takar
    BEGIN
187
        IF s = '1' THEN
188
            -- left arithmetic or logical shift
189
            RETURN shift_left(value, shamt);
190
        ELSE
191
            IF t = '1' THEN
192
                -- right arithmetic shift
193
                RETURN shift_right(value, shamt, value(31));
194
            ELSE
195
                -- right logical shift
196
                RETURN shift_right(value, shamt, '0');
197
            END IF;
198
        END IF;
199
    END;
200
 
201 6 takar
    FUNCTION shift_left(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector IS
202
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
203
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
204 2 takar
    BEGIN
205
 
206
        paddings := (OTHERS => '0');
207
        result := value;
208
        IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
209
        IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
210
        IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
211
        IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
212
        IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 );         END IF;
213
        RETURN result;
214
 
215
    END;
216
 
217 6 takar
    FUNCTION shift_right(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector IS
218
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
219
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
220 2 takar
    BEGIN
221
 
222
        paddings := (OTHERS => padding);
223
        result := value;
224
        IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
225
        IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO  8); END IF;
226
        IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO  4); END IF;
227
        IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO  2); END IF;
228
        IF (shamt(0) = '1') THEN result := paddings( 0 )         & result(31 DOWNTO  1); END IF;
229
        RETURN result;
230
 
231
    END;
232
 
233 6 takar
    FUNCTION multiply(a, b: std_logic_vector) RETURN std_logic_vector IS
234
        VARIABLE x: std_logic_vector (a'length + b'length - 1 DOWNTO 0);
235 2 takar
    BEGIN
236 6 takar
        x := std_logic_vector(signed(a) * signed(b));
237 2 takar
        RETURN x(31 DOWNTO 0);
238
    END;
239
 
240 6 takar
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector IS
241
        VARIABLE a: std_logic_vector (size - 1 DOWNTO 0);
242 2 takar
    BEGIN
243
        a(size - 1 DOWNTO value'length) := (OTHERS => fill);
244
        a(value'length - 1 DOWNTO 0) := value;
245
        return a;
246
    END;
247
 
248 6 takar
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector IS
249
        VARIABLE x : std_logic_vector(a'length + 1 DOWNTO 0);
250 2 takar
    BEGIN
251
        x := (OTHERS => '0');
252
        IF notx (a & b & ci) THEN
253 6 takar
            x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
254 2 takar
        END IF;
255
        RETURN x(a'length + 1 DOWNTO 1);
256
    END;
257
 
258 6 takar
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector IS
259
        VARIABLE x : std_logic_vector(a'length-1 DOWNTO 0);
260 2 takar
    BEGIN
261
        x := (OTHERS => '0');
262
        IF notx (a) THEN
263 6 takar
            x := std_logic_vector(signed(a) + 1);
264 2 takar
        END IF;
265
        RETURN x;
266
    END;
267
 
268
END std_Pkg;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.