URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [tb/] [rom_fwd_hzd.mem] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	takar	`// memory data file (do not edit the following line - required for mem load use)`
2			`// LW R1, R3, R4 => R1 = 0x0EF`
3			`// ADD R5, R1, R2 => R5 = 0x0F1 => HZD + WB FWD A`
4			`// ADD R1, R1, R2 => R1 = 0x0F1 => WB FWD A`
5			`// ADD R1, R1, R3 => R1 = 0x0F4 => EX FWD A`
6			`// ADD R1, R1, R4 => R1 = 0x0F8 => EX FWD A`
7			`// NOP`
8			`// ADD R1, R1, R5 => R1 = 0x1E9 => WB FWD A`
9			`// NOP`
10			`// NOP`
11			`// LW R1, R3, R4 => R1 = 0x0EF`
12			`// ADD R5, R2, R1 => R5 = 0x0F1 => HZD + WB FWD B`
13			`// ADD R1, R2, R1 => R1 = 0x0F1 => WB FWD B`
14			`// ADD R1, R3, R1 => R1 = 0x0F4 => EX FWD B`
15			`// ADD R1, R4, R1 => R1 = 0x0F8 => EX FWD B`
16			`// NOP`
17			`// ADD R1, R5, R1 => R1 = 0x1E9 => WB FWD B`
18			`// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1`
19			`@00000000`
20			`C82E7000`
21			`00A11000`
22			`00211000`
23			`00211800`
24			`00212000`
25			`00000000`
26			`00212800`
27			`00000000`
28			`00000000`
29			`C82E7000`
30			`00A20800`
31			`00220800`
32			`00230800`
33			`00240800`
34			`00000000`
35			`00250800`