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mezzah |
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-- Company: Ferhat Abbas University - Algeria
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-- Engineer: Ibrahim MEZZAH
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-- Progect Supervisor: Dr H. Chemali
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-- Create Date: 01:15:35 07/17/05
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-- Design Name: 8-bits arithmetic and logic unit (2)
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-- Module Name: ALU - simple
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-- Project Name: Microcontroller IP (MCIP)
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-- Target Device: xc3s500e-4fg320
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-- Tool versions: Xilinx ISE 9.1.03i
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-- Description: This ALU is based on 8 simple slices. This module:
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-- operates on A, B and using Old status,
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-- provides the result S and the New status.
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-- Revision: 07/07/2008
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-- Revision 2.2 - Add description
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ALU is
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Port ( CommandVector : in std_logic_vector(13 downto 0);
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CommandStatus : in std_logic_vector(4 downto 0);
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OldStatus : in std_logic_vector(4 downto 0);
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a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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s : out std_logic_vector(7 downto 0);
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NewStatus : out std_logic_vector(4 downto 0);
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SetResponse : out std_logic_vector(1 downto 0));
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end ALU;
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architecture simple of ALU is
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component alu_slice
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Port ( g : in std_logic_vector(3 downto 0);
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p : in std_logic_vector(3 downto 0);
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a : in std_logic;
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b : in std_logic;
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ci : in std_logic;
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s : out std_logic;
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co : out std_logic);
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end component;
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signal ci : std_logic_vector(7 downto 0);
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signal co : std_logic_vector(7 downto 0);
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signal ai : std_logic_vector(7 downto 0);
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signal bi : std_logic_vector(7 downto 0);
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signal si : std_logic_vector(7 downto 0);
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signal CurrentStatus : std_logic_vector(4 downto 0);
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signal cr0 : std_logic;
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signal cr7 : std_logic;
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signal C : std_logic;
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signal DC : std_logic;
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signal Z : std_logic;
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signal OV : std_logic;
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signal N : std_logic;
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signal test_bit : std_logic;
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signal SWAPa : std_logic_vector(7 downto 0);
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signal S_D : std_logic_vector(7 downto 0);
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signal BITOPa : std_logic_vector(7 downto 0);
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signal DAW_op : std_logic_vector(7 downto 0);
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alias v : std_logic_vector(13 downto 0) is CommandVector;
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begin
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slices: for i in 0 to 7 generate
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slice: alu_slice
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port map( g => v(3 downto 0),
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p => v(7 downto 4),
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a => ai(i),
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b => bi(i),
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ci => ci(i),
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s => si(i),
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co => co(i)
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);
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end generate;
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cr0 <= a(1) when v(11) = '1' else
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a(7);
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cr7 <= a(0) when v(10) = '1' else
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OldStatus(0);
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ci(0) <= '0' when v(13 downto 12) = "00" else
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'1' when v(13 downto 12) = "01" else
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cr0 when v(13 downto 12) = "10" else
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OldStatus(0);
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ci(7) <= cr7 when v(11) = '1' else
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co(6);
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C <= co(0) when v(11) = '1' else
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co(7);
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DC <= ci(4);
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Z <= '1' when si = X"00" else
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'0';
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N <= si(7);
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OV <= '1'
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when((v(0)='0' and v(1)='1' and N='1' and a(7)='0' and b(7)='0') or
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(v(0)='0' and v(1)='1' and N='0' and a(7)='1' and b(7)='1') or
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(v(0)='0' and v(1)='0' and N='1' and a(7)='0') or
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(v(0)='1' and v(1)='0' and v(5)='0' and N='0' and a(7)='1' and b(7)='0') or
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(v(0)='1' and v(1)='0' and v(5)='0' and N='1' and a(7)='0' and b(7)='1') or
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(v(0)='1' and v(7)='1' and N='0' and a(7)='1') or
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(v(0)='1' and v(1)='0' and v(5)='1' and N='1' and a(7)='1' and b(7)='0') or
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(v(0)='1' and v(1)='0' and v(5)='1' and N='0' and a(7)='0' and b(7)='1') or
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(v(0)='1' and v(1)='1' and v(7)='0' and N='1' and a(7)='1') ) else
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'0';
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CurrentStatus <= N&OV&Z&DC&C;
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SWAPa <= a(3 downto 0) & a(7 downto 4);
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DAW_op(3 downto 0) <= X"6"
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when ((b(3 downto 0) > "1001") or OldStatus(1)='1') else
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X"0";
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DAW_op(7 downto 4) <= X"6" when ((b(7 downto 4) > "1001") or OldStatus(0)='1'
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or (b(7 downto 4)="1001" and DC='1')) else
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X"0";
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S_D <= DAW_op when V(10) = '0' else
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SWAPa;
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ai <= BITOPa when v(8) = '0' else
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S_D when v(9) = '0' else
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a;
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bi <= b;
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SetResponse(0) <= test_bit when v(8) = '0' else
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N;
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SetResponse(1) <= Z;
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Carry : process(v(13 downto 11), a, co, cr0, cr7, OldStatus(0))
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begin
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for i in 0 to 7 loop
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if i = 0 then
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if v(13 downto 12) = "00" then
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ci(i) <= '0';
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elsif v(13 downto 12) = "01" then
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ci(i) <= '1';
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elsif v(13 downto 12) = "10" then
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ci(i) <= cr0;
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else
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ci(i) <= OldStatus(0);
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end if;
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elsif i = 7 then
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if v(11) = '1' then
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ci(i) <= cr7;
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else
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ci(i) <= co(6);
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end if;
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else
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if v(11) = '1' then
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ci(i) <= a(i+1);
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else
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ci(i) <= co(i-1);
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end if;
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end if;
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end loop;
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end process;
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Bit_op : process(a, b(2 downto 0), v(10 downto 9))
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begin
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for i in 0 to 7 loop
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if i = conv_integer(b(2 downto 0)) then
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if v(9) = '1' then
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BITOPa(i) <= not a(i);
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elsif v(10) = '0' then
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BITOPa(i) <= '0';
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else
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BITOPa(i) <= '1';
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end if;
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test_bit <= a(i);
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else
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BITOPa(i) <= a(i);
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end if;
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end loop;
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end process;
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Status : process(OldStatus, CommandStatus, CurrentStatus)
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begin
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for i in 0 to 4 loop
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if CommandStatus(i) = '1' then
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NewStatus(i) <= CurrentStatus(i);
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else
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NewStatus(i) <= OldStatus(i);
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end if;
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end loop;
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end process;
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s <= si;
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end simple;
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