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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Data_Memory_Banks_Controller.vhd] - Blame information for rev 4

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1 4 mezzah
----------------------------------------------------------------------------------
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-- Company:        Ferhat Abbas University - Algeria
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-- Engineer:       Ibrahim MEZZAH
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-- 
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-- Create Date:    10:09:19 04/17/2012 
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-- Design Name: 
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-- Module Name:    Data_Memory_Controller - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Data_Memory_Banks_Controller is
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         Generic (Banks_number          : integer := 3; -- number of banks, min = 2, max = 16
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                                 dm_TOPaddr                     : std_logic_vector(11 downto 0) := x"07F");
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    Port ( RE                                           : in std_logic;
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           WE                                           : in std_logic;
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                          Data_address                  : in std_logic_vector(11 downto 0);
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           RE_bank                              : out std_logic;
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           WE_bank                              : out std_logic;
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           Bank_selection               : out std_logic_vector(0 to Banks_number-1);
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           Bank_data_address    : out std_logic_vector(7 downto 0)
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                          );
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end Data_Memory_Banks_Controller;
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architecture Behavioral of Data_Memory_Banks_Controller is
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        signal over_address : std_logic;
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begin
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        over_address <= '1'                             when Data_Address > dm_TOPaddr else
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                                                 '0';
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        RE_bank <= RE                                           when over_address = '0' else '0';
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        WE_bank <= WE                                           when over_address = '0' else '0';
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        Bank_data_address <= Data_address(7 downto 0);
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        Bank_selection_p : process(Data_address(11 downto 8))
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        begin
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                for i in 0 to Banks_number-1 loop
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                        if i = CONV_INTEGER(Data_address(11 downto 8)) then
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                                Bank_selection(i)  <= '1';
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                        else
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                                Bank_selection(i)  <= '0';
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                        end if;
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                end loop;
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        end process;
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end Behavioral;
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