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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Instruction_Decoder.vhd] - Blame information for rev 4

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--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    00:56:38 06/04/05
-- Design Name:    Instruction decoder and control
-- Module Name:    InstructionDecoder_Control - Decode_Cotrol
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:  Decodes the fetched instruction and selects the block
--                 concernrd by read and write operations.
-- Revision:             07/07/2008
-- Revision  2.2 - Add description
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Instruction_Decoder is
    Port ( nreset            : in std_logic;
                          Q1                : in std_logic;
                          Q4                : in std_logic;
                          Fetched_instruction : in std_logic_vector(15 downto 0);
                          Data_add          : in std_logic_vector(11 downto 0);
                          New_status        : in std_logic_vector(4 downto 0);
                          Set_response      : in std_logic_vector(1 downto 0);
                          Data              : inout std_logic_vector(7 downto 0);
 
                          Command_vector_opu : out std_logic_vector(13 downto 0);
                          Command_vector_pc : out std_logic_vector(6 downto 0);
                          Command_status    : out std_logic_vector(4 downto 0);
                          Current_status    : out std_logic_vector(4 downto 0);
                          Bit_op            : out std_logic_vector(2 downto 0);
                          call_return       : out std_logic_vector(1 downto 0);
                          IR11_0            : out std_logic_vector(11 downto 0);
                          r_w_ram           : out std_logic_vector(1 downto 0);
                          r_w_add_pr        : out std_logic_vector(1 downto 0);
                          r_w_opu            : out std_logic_vector(1 downto 0);
                          r_w_port          : out std_logic_vector(1 downto 0);
                          r_w_wdt           : out std_logic_vector(1 downto 0);
                          bit_op_enable     : out std_logic;
                          load_FREG         : out std_logic;
                          read_result       : out std_logic;
                          WREG_write_enable : out std_logic;
                          MUL_enable        : out std_logic;
                          MOVFF_enable      : out std_logic;
                          load_BSR          : out std_logic;
                          soft_reset_enable : out std_logic;
                          sleep_mode_enable : out std_logic;
                          clear_watchdog    : out std_logic
);
end Instruction_Decoder;
 
architecture Decode_Control of Instruction_Decoder is
 
component Decoder
    Port ( Instruction       : in std_logic_vector(15 downto 0);
                          Status            : in std_logic_vector(4 downto 1);
                          second_inst_ide   : in std_logic_vector(2 downto 0);
                          Command_vector_pc : out std_logic_vector(6 downto 0);
                          Command_vector_opu : out std_logic_vector(13 downto 0);
                          Command_status    : out std_logic_vector(4 downto 0);
                          second_inst_inf   : out std_logic_vector(2 downto 0);
                          Skip_inf          : out std_logic_vector(4 downto 0);
                          read_write        : out std_logic_vector(1 downto 0);
                          call_return       : out std_logic_vector(1 downto 0);
                          bit_op_enable     : out std_logic;
                          load_FREG         : out std_logic;
                          read_result       : out std_logic;
                          WREG_write_enable : out std_logic;
                          MUL_enable        : out std_logic;
                          MOVFF_enable      : out std_logic;
                          load_BSR          : out std_logic;
                          nop_enable        : out std_logic;
                          soft_reset_enable : out std_logic;
                          sleep_mode_enable : out std_logic;
                          clear_watchdog    : out std_logic;
                          literal_enable    : out std_logic );
end component Decoder;
 
--component Instruction_Control
--    Port ( nreset             : in std_logic;
--           Q1                 : in std_logic;
--           Fetched_instruction  : in std_logic_vector(15 downto 0);
--           Set_response       : in std_logic_vector(1 downto 0);
--           Skip_info          : in std_logic_vector(4 downto 0);
--           nop_enable         : in std_logic;
--           retfie             : in std_logic;
--           INTH               : in std_logic;
--           INTL               : in std_logic;
--           GIEH               : in std_logic;
--           GIEL               : in std_logic;
--           second_inst_enable : in std_logic;
--           freeze_enable      : out std_logic;
--           GIEHout            : out std_logic;
--           GIELout            : out std_logic;
--           load_INTCON        : out std_logic;
--           Instruction        : out std_logic_vector(15 downto 0) );
--end component Instruction_Control;
 
component Selection_block
    Port ( R_W        : in std_logic_vector(1 downto 0);
                          Address    : in  std_logic_vector(11 downto 0);
                          r_w_ram    : out std_logic_vector(1 downto 0);
                          r_w_add_pr : out std_logic_vector(1 downto 0);
                          r_w_opu    : out std_logic_vector(1 downto 0);
                          r_w_port   : out std_logic_vector(1 downto 0);
                          r_w_dec    : out std_logic_vector(1 downto 0);
                          r_w_wdt    : out std_logic_vector(1 downto 0) );
end component Selection_block;
 
--component Interrupt_Block
--    Port ( INTCON  : in std_logic_vector(7 downto 0);
--           INTCON2 : in std_logic_vector(7 downto 0);
--           INTCON3 : in std_logic_vector(1 downto 0);
--           INTH    : out std_logic;
--           INTL    : out std_logic;
--           wake_up : out std_logic);
--end component Interrupt_Block;
 
  signal data_read  : std_logic_vector(7 downto 0);
 
  signal IR : std_logic_vector(15 downto 0);
  signal instruction : std_logic_vector(15 downto 0);
 
  signal STATUS      : std_logic_vector(4 downto 0);
  signal STATUSs     : std_logic_vector(4 downto 0);
  signal STATUSmap   : std_logic_vector(4 downto 1);
 
  signal literal_enable : std_logic;
  signal nop_enable     : std_logic;
  signal sleep_mode_enables : std_logic;
 
  signal Set_response_register : std_logic_vector(1 downto 0);
  signal Command_status_s      : std_logic_vector(4 downto 0);
 
  signal R_W     : std_logic_vector(1 downto 0);
  signal r_w_dec : std_logic_vector(1 downto 0);
 
  signal second_inst_register  : std_logic_vector(2 downto 0);
  signal second_inst_inf       : std_logic_vector(2 downto 0);
  signal Skip_inf      : std_logic_vector(4 downto 0);
  signal call_returns          : std_logic_vector(1 downto 0);
 
  signal nop_enables : std_logic;
 
  alias read_en    : std_logic is r_w_dec(1);
  alias write_en   : std_logic is r_w_dec(0);
 
 
begin
 
ins_decoder : Decoder
Port map ( Instruction       => IR,
                          Status            => STATUSmap,
                          second_inst_ide   => second_inst_register,
                          Command_vector_pc => Command_vector_pc,
                          Command_vector_opu => Command_vector_opu,
                          Command_status    => Command_status_s,
                          second_inst_inf   => second_inst_inf,
                          Skip_inf          => Skip_inf,
                          read_write        => R_W,
                          call_return       => call_returns,
                          bit_op_enable     => bit_op_enable,
                          load_FREG         => load_FREG,
                          read_result       => read_result,
                          WREG_write_enable => WREG_write_enable,
                          MUL_enable        => MUL_enable,
                          MOVFF_enable      => MOVFF_enable,
                          load_BSR          => load_BSR,
                          nop_enable        => nop_enable,
                          soft_reset_enable => soft_reset_enable,
                          sleep_mode_enable => sleep_mode_enables,
                          clear_watchdog    => clear_watchdog,
                          literal_enable    => literal_enable );
 
 
selecter : Selection_Block
Port map ( R_W        => R_W,
                          Address    => Data_add,
                          r_w_ram    => r_w_ram,
                          r_w_add_pr => r_w_add_pr,
                          r_w_opu    => r_w_opu,
                          r_w_port   => r_w_port,
                          r_w_dec    => r_w_dec,
                          r_w_wdt    => r_w_wdt );
 
 
        nop_enables <= '1'              when (nop_enable = '1' or (Skip_inf(4) = '1' and
                                (Skip_inf(3 downto 2)=(Skip_inf(1 downto 0) and Set_response_register)))) else
                                                '0';
 
        instruction <= X"F000" when nop_enables = '1' else Fetched_instruction;
 
 
        data_read <= IR(7 downto 0)                              when literal_enable='1' else
                                         "000"&STATUS;
        Data <= data_read                                       when (read_en='1' or literal_enable='1')and Q1='1'else
                          (others => 'Z');
        sleep_mode_enable <= sleep_mode_enables;
        Command_status <= Command_status_s;
        STATUSmap      <= STATUS(4 downto 2)&STATUS(0);
        Current_status <= STATUS;
        Bit_op      <= IR(11 downto 9);
        call_return <= call_returns;
        IR11_0      <= IR(11 downto 0);
 
 
        process(nreset, Q1, instruction, second_inst_inf)
                begin
                  if nreset = '0' then
                         IR <= (others => '0');
                         second_inst_register <= (others => '0');
                  else
                         if Q1'event and Q1 = '1' then
                                IR <= instruction;
                                second_inst_register <= second_inst_inf;
                         end if;
                  end if;
                end process;
 
        process(nreset, Q4, write_en, Data,
                          Set_response, call_returns, STATUS, STATUSs)
                begin
                  if nreset = '0' then
                         STATUS  <= (others => '0');
                         STATUSs <= (others => '0');
                         Set_response_register <= (others => '0');
                  else
                         if Q4'event and Q4 = '1' then
                                Set_response_register <= Set_response;
                                if write_en = '1' and Command_status_s = "00000" then
                                        STATUS <= Data(4 downto 0);
                                else
                                  if call_returns(1) = '1' then
                                        if call_returns(0) = '0' then
                                          STATUSs <= STATUS;                            -- call
                                        else
                                          STATUS  <= STATUSs;                   -- return
                                        end if;
                                  else
                                          STATUS  <= New_status;
                                  end if;
                                end if;
                         end if;
                  end if;
                end process;
 
end Decode_Control;

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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Instruction_Decoder.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	mezzah	`--------------------------------------------------------------------------------`
2			`-- Company: Ferhat Abbas University - Algeria`
3			`-- Engineer: Ibrahim MEZZAH`
4			`-- Progect Supervisor: Dr H. Chemali`
5			`-- Create Date: 00:56:38 06/04/05`
6			`-- Design Name: Instruction decoder and control`
7			`-- Module Name: InstructionDecoder_Control - Decode_Cotrol`
8			`-- Project Name: Microcontroller IP (MCIP)`
9			`-- Target Device: xc3s500e-4fg320`
10			`-- Tool versions: Xilinx ISE 9.1.03i`
11			`-- Description: Decodes the fetched instruction and selects the block`
12			`-- concernrd by read and write operations.`
13			`-- Revision: 07/07/2008`
14			`-- Revision 2.2 - Add description`
15			`--------------------------------------------------------------------------------`
16			`library IEEE;`
17			`use IEEE.STD_LOGIC_1164.ALL;`
18			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
19
20			`entity Instruction_Decoder is`
21			`Port ( nreset : in std_logic;`
22			`Q1 : in std_logic;`
23			`Q4 : in std_logic;`
24			`Fetched_instruction : in std_logic_vector(15 downto 0);`
25			`Data_add : in std_logic_vector(11 downto 0);`
26			`New_status : in std_logic_vector(4 downto 0);`
27			`Set_response : in std_logic_vector(1 downto 0);`
28			`Data : inout std_logic_vector(7 downto 0);`
29
30			`Command_vector_opu : out std_logic_vector(13 downto 0);`
31			`Command_vector_pc : out std_logic_vector(6 downto 0);`
32			`Command_status : out std_logic_vector(4 downto 0);`
33			`Current_status : out std_logic_vector(4 downto 0);`
34			`Bit_op : out std_logic_vector(2 downto 0);`
35			`call_return : out std_logic_vector(1 downto 0);`
36			`IR11_0 : out std_logic_vector(11 downto 0);`
37			`r_w_ram : out std_logic_vector(1 downto 0);`
38			`r_w_add_pr : out std_logic_vector(1 downto 0);`
39			`r_w_opu : out std_logic_vector(1 downto 0);`
40			`r_w_port : out std_logic_vector(1 downto 0);`
41			`r_w_wdt : out std_logic_vector(1 downto 0);`
42			`bit_op_enable : out std_logic;`
43			`load_FREG : out std_logic;`
44			`read_result : out std_logic;`
45			`WREG_write_enable : out std_logic;`
46			`MUL_enable : out std_logic;`
47			`MOVFF_enable : out std_logic;`
48			`load_BSR : out std_logic;`
49			`soft_reset_enable : out std_logic;`
50			`sleep_mode_enable : out std_logic;`
51			`clear_watchdog : out std_logic`
52			`);`
53			`end Instruction_Decoder;`
54
55			`architecture Decode_Control of Instruction_Decoder is`
56
57			`component Decoder`
58			`Port ( Instruction : in std_logic_vector(15 downto 0);`
59			`Status : in std_logic_vector(4 downto 1);`
60			`second_inst_ide : in std_logic_vector(2 downto 0);`
61			`Command_vector_pc : out std_logic_vector(6 downto 0);`
62			`Command_vector_opu : out std_logic_vector(13 downto 0);`
63			`Command_status : out std_logic_vector(4 downto 0);`
64			`second_inst_inf : out std_logic_vector(2 downto 0);`
65			`Skip_inf : out std_logic_vector(4 downto 0);`
66			`read_write : out std_logic_vector(1 downto 0);`
67			`call_return : out std_logic_vector(1 downto 0);`
68			`bit_op_enable : out std_logic;`
69			`load_FREG : out std_logic;`
70			`read_result : out std_logic;`
71			`WREG_write_enable : out std_logic;`
72			`MUL_enable : out std_logic;`
73			`MOVFF_enable : out std_logic;`
74			`load_BSR : out std_logic;`
75			`nop_enable : out std_logic;`
76			`soft_reset_enable : out std_logic;`
77			`sleep_mode_enable : out std_logic;`
78			`clear_watchdog : out std_logic;`
79			`literal_enable : out std_logic );`
80			`end component Decoder;`
81
82			`--component Instruction_Control`
83			`-- Port ( nreset : in std_logic;`
84			`-- Q1 : in std_logic;`
85			`-- Fetched_instruction : in std_logic_vector(15 downto 0);`
86			`-- Set_response : in std_logic_vector(1 downto 0);`
87			`-- Skip_info : in std_logic_vector(4 downto 0);`
88			`-- nop_enable : in std_logic;`
89			`-- retfie : in std_logic;`
90			`-- INTH : in std_logic;`
91			`-- INTL : in std_logic;`
92			`-- GIEH : in std_logic;`
93			`-- GIEL : in std_logic;`
94			`-- second_inst_enable : in std_logic;`
95			`-- freeze_enable : out std_logic;`
96			`-- GIEHout : out std_logic;`
97			`-- GIELout : out std_logic;`
98			`-- load_INTCON : out std_logic;`
99			`-- Instruction : out std_logic_vector(15 downto 0) );`
100			`--end component Instruction_Control;`
101
102			`component Selection_block`
103			`Port ( R_W : in std_logic_vector(1 downto 0);`
104			`Address : in std_logic_vector(11 downto 0);`
105			`r_w_ram : out std_logic_vector(1 downto 0);`
106			`r_w_add_pr : out std_logic_vector(1 downto 0);`
107			`r_w_opu : out std_logic_vector(1 downto 0);`
108			`r_w_port : out std_logic_vector(1 downto 0);`
109			`r_w_dec : out std_logic_vector(1 downto 0);`
110			`r_w_wdt : out std_logic_vector(1 downto 0) );`
111			`end component Selection_block;`
112
113			`--component Interrupt_Block`
114			`-- Port ( INTCON : in std_logic_vector(7 downto 0);`
115			`-- INTCON2 : in std_logic_vector(7 downto 0);`
116			`-- INTCON3 : in std_logic_vector(1 downto 0);`
117			`-- INTH : out std_logic;`
118			`-- INTL : out std_logic;`
119			`-- wake_up : out std_logic);`
120			`--end component Interrupt_Block;`
121
122			`signal data_read : std_logic_vector(7 downto 0);`
123
124			`signal IR : std_logic_vector(15 downto 0);`
125			`signal instruction : std_logic_vector(15 downto 0);`
126
127			`signal STATUS : std_logic_vector(4 downto 0);`
128			`signal STATUSs : std_logic_vector(4 downto 0);`
129			`signal STATUSmap : std_logic_vector(4 downto 1);`
130
131			`signal literal_enable : std_logic;`
132			`signal nop_enable : std_logic;`
133			`signal sleep_mode_enables : std_logic;`
134
135			`signal Set_response_register : std_logic_vector(1 downto 0);`
136			`signal Command_status_s : std_logic_vector(4 downto 0);`
137
138			`signal R_W : std_logic_vector(1 downto 0);`
139			`signal r_w_dec : std_logic_vector(1 downto 0);`
140
141			`signal second_inst_register : std_logic_vector(2 downto 0);`
142			`signal second_inst_inf : std_logic_vector(2 downto 0);`
143			`signal Skip_inf : std_logic_vector(4 downto 0);`
144			`signal call_returns : std_logic_vector(1 downto 0);`
145
146			`signal nop_enables : std_logic;`
147
148			`alias read_en : std_logic is r_w_dec(1);`
149			`alias write_en : std_logic is r_w_dec(0);`
150
151
152			`begin`
153
154			`ins_decoder : Decoder`
155			`Port map ( Instruction => IR,`
156			`Status => STATUSmap,`
157			`second_inst_ide => second_inst_register,`
158			`Command_vector_pc => Command_vector_pc,`
159			`Command_vector_opu => Command_vector_opu,`
160			`Command_status => Command_status_s,`
161			`second_inst_inf => second_inst_inf,`
162			`Skip_inf => Skip_inf,`
163			`read_write => R_W,`
164			`call_return => call_returns,`
165			`bit_op_enable => bit_op_enable,`
166			`load_FREG => load_FREG,`
167			`read_result => read_result,`
168			`WREG_write_enable => WREG_write_enable,`
169			`MUL_enable => MUL_enable,`
170			`MOVFF_enable => MOVFF_enable,`
171			`load_BSR => load_BSR,`
172			`nop_enable => nop_enable,`
173			`soft_reset_enable => soft_reset_enable,`
174			`sleep_mode_enable => sleep_mode_enables,`
175			`clear_watchdog => clear_watchdog,`
176			`literal_enable => literal_enable );`
177
178
179			`selecter : Selection_Block`
180			`Port map ( R_W => R_W,`
181			`Address => Data_add,`
182			`r_w_ram => r_w_ram,`
183			`r_w_add_pr => r_w_add_pr,`
184			`r_w_opu => r_w_opu,`
185			`r_w_port => r_w_port,`
186			`r_w_dec => r_w_dec,`
187			`r_w_wdt => r_w_wdt );`
188
189
190			`nop_enables <= '1' when (nop_enable = '1' or (Skip_inf(4) = '1' and`
191			`(Skip_inf(3 downto 2)=(Skip_inf(1 downto 0) and Set_response_register)))) else`
192			`'0';`
193
194			`instruction <= X"F000" when nop_enables = '1' else Fetched_instruction;`
195
196
197			`data_read <= IR(7 downto 0) when literal_enable='1' else`
198			`"000"&STATUS;`
199			`Data <= data_read when (read_en='1' or literal_enable='1')and Q1='1'else`
200			`(others => 'Z');`
201			`sleep_mode_enable <= sleep_mode_enables;`
202			`Command_status <= Command_status_s;`
203			`STATUSmap <= STATUS(4 downto 2)&STATUS(0);`
204			`Current_status <= STATUS;`
205			`Bit_op <= IR(11 downto 9);`
206			`call_return <= call_returns;`
207			`IR11_0 <= IR(11 downto 0);`
208
209
210			`process(nreset, Q1, instruction, second_inst_inf)`
211			`begin`
212			`if nreset = '0' then`
213			`IR <= (others => '0');`
214			`second_inst_register <= (others => '0');`
215			`else`
216			`if Q1'event and Q1 = '1' then`
217			`IR <= instruction;`
218			`second_inst_register <= second_inst_inf;`
219			`end if;`
220			`end if;`
221			`end process;`
222
223			`process(nreset, Q4, write_en, Data,`
224			`Set_response, call_returns, STATUS, STATUSs)`
225			`begin`
226			`if nreset = '0' then`
227			`STATUS <= (others => '0');`
228			`STATUSs <= (others => '0');`
229			`Set_response_register <= (others => '0');`
230			`else`
231			`if Q4'event and Q4 = '1' then`
232			`Set_response_register <= Set_response;`
233			`if write_en = '1' and Command_status_s = "00000" then`
234			`STATUS <= Data(4 downto 0);`
235			`else`
236			`if call_returns(1) = '1' then`
237			`if call_returns(0) = '0' then`
238			`STATUSs <= STATUS; -- call`
239			`else`
240			`STATUS <= STATUSs; -- return`
241			`end if;`
242			`else`
243			`STATUS <= New_status;`
244			`end if;`
245			`end if;`
246			`end if;`
247			`end if;`
248			`end process;`
249
250			`end Decode_Control;`