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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [MCIPopen_mcu_example.vhd] - Blame information for rev 4

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:09:51 07/24/2015 
-- Design Name: 
-- Module Name:    MCIPopen_mcu_example - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity MCIPopen_mcu_example is
         Generic (      STKPTR_length   : integer := 5;         -- Stack Pointer Length --> min = 2, max = 5
                                        STVREN                  : std_logic := '1';     -- Stack Overflow/Underflow Reset Enable bit
 
                                        WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
                                        WDTEN : std_logic := '0'; -- Watchdog Timer enable bit
 
                                        Banks_number            : integer := 3; -- number of banks, min = 2, max = 16
                                        dm_TOPaddr                      : std_logic_vector(11 downto 0) := x"2FF";
 
                                        IAlength                : integer := 12; -- min = 2, max = 21
                                        pm_TOPaddr              : std_logic_vector(20 downto 0) := '0'&x"03FFF"
                                        );
 
    Port ( nreset             : in std_logic;
           clk25MHz           : in std_logic;
                          Wdt_clock                             : in std_logic;
                          clock_out          : out std_logic;
           PORTA              : inout std_logic_vector(7 downto 0);
           PORTB              : inout std_logic_vector(7 downto 0);
           PORTC              : inout std_logic_vector(7 downto 0);
           PORTD              : inout std_logic_vector(7 downto 0) );
end MCIPopen_mcu_example;
 
architecture Behavioral of MCIPopen_mcu_example is
 
component MCIPopen is
    Generic ( STKPTR_length : integer := 5;  -- Stack Pointer Length -- < 6
                                  STVREN : std_logic := '1';    -- Stack Overflow/Underflow Reset Enable bit
                                  WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
                                  WDTEN : std_logic := '0'); -- Watchdog Timer enable bit
    Port ( nreset             : in std_logic;
           clock              : in std_logic;
                          Wdt_clock                             : in std_logic;
           Instruction        : in std_logic_vector(15 downto 0);
                          clock_out          : out std_logic;
                          nresetDevice       : out std_logic;
                          Q1                 : out std_logic;
                          Q4                 : out std_logic;
                          RE_ram             : out std_logic;
                          WE_ram             : out std_logic;
           Istruction_address : out std_logic_vector(20 downto 0);
           Data_address       : out std_logic_vector(11 downto 0);
           Data_Bus           : inout std_logic_vector(7 downto 0);
           PORTA              : inout std_logic_vector(7 downto 0);
           PORTB              : inout std_logic_vector(7 downto 0);
           PORTC              : inout std_logic_vector(7 downto 0);
           PORTD              : inout std_logic_vector(7 downto 0) );
end component MCIPopen;
 
 
component Data_Memory_Banks_Controller is
         Generic (Banks_number          : integer := Banks_number;      -- number of banks, min = 2, max = 16
                                 dm_TOPaddr                     : std_logic_vector(11 downto 0) := dm_TOPaddr);
    Port ( RE                                           : in std_logic;
           WE                                           : in std_logic;
                          Data_address                  : in std_logic_vector(11 downto 0);
--           DATA                                       : inout std_logic_vector(7 downto 0);
 
           RE_bank                              : out std_logic;
           WE_bank                              : out std_logic;
           Bank_selection               : out std_logic_vector(0 to Banks_number-1);
           Bank_data_address    : out std_logic_vector(7 downto 0)
--           Bank_data                  : inout std_logic_vector(7 downto 0)
                          );
end component Data_Memory_Banks_Controller;
 
component Memory_bank is
    Port ( Address : in std_logic_vector(7 downto 0);
           enable  : in std_logic;
           RE      : in std_logic;
                          WE      : in std_logic;
           Q1      : in std_logic;
           Q4      : in std_logic;
           DATA    : inout std_logic_vector(7 downto 0));
end component Memory_bank;
 
component Program_Memory_Controller is
         Generic (IAlength              : integer := IAlength; -- min = 2, max = 21
                                 pm_TOPaddr             : std_logic_vector(20 downto 0) := pm_TOPaddr);
    Port ( Prg_addr                     : in std_logic_vector(20 downto 0);
                          Instruction           : out std_logic_vector(15 downto 0);
 
                          eff_Prg_addr          : out std_logic_vector(IAlength-1 downto 0);
                          Prg_memory_bus        : in std_logic_vector(15 downto 0));
end component Program_Memory_Controller;
 
component Program_Memory is
         Generic (IAlength              : integer := IAlength);  -- Instruction Address Length -- min = 2, max = 21
    Port ( Address : in std_logic_vector(IALength-1 downto 0);
           nreset  : in std_logic;
           Q1      : in std_logic;
           Instruction : out std_logic_vector(15 downto 0));
end component Program_Memory;
 
--      signal clk_2                            : std_logic;
--      signal clk_3                            : std_logic_vector(1 downto 0);
 
        signal mcu_nreset                       : std_logic;
--      signal internal_clock   : std_logic;
        signal Q1                                       : std_logic;
        signal Q4                                       : std_logic;
 
--      signal Data_addr                        : std_logic_vector(11 downto 0);
        signal Data_bus                 : std_logic_vector(7 downto 0);
--      signal mcu_RE                           : std_logic;
--      signal mcu_WE                           : std_logic;
 
--      signal RE_intr_con              : std_logic;
--      signal WE_intr_con              : std_logic;
--      signal SFR_address_intr_con: std_logic_vector(4 downto 0);
 
        signal Prg_addr                 : std_logic_vector(20 downto 0);
        signal Inst_bus                 : std_logic_vector(15 downto 0);
 
        signal eff_Prg_addr             : std_logic_vector(IAlength-1 downto 0);
        signal Prg_memory_bus   : std_logic_vector(15 downto 0);
 
--      signal enable_sleep             : std_logic;
--      signal WDTwake_up                       : std_logic;
--      signal sleep_enabled            : std_logic;
 
--      signal INTH                                     : std_logic;
--      signal INTL                                     : std_logic;
--      signal GIE                                      : std_logic;
--      signal GIEL                                     : std_logic;
--      signal GIEHfeedback             : std_logic;
--      signal GIELfeedback             : std_logic;
--      signal load_INTCON              : std_logic;
--      signal IPEN                                     : std_logic;
--
--      signal Interrupt                        : std_logic_vector(1 to Intr_Nbr);
--      signal Interrupt_ack            : std_logic_vector(1 to Intr_Nbr);
--
--      signal PORTC_addr                       : std_logic_vector(3 downto 0);
--      signal RE_PORTC                 : std_logic;
--      signal WE_PORTC                 : std_logic;
--
--      signal PORTD_addr                       : std_logic_vector(3 downto 0);
--      signal RE_PORTD                 : std_logic;
--      signal WE_PORTD                 : std_logic;
--
--      signal Timer2_addr              : std_logic_vector(1 downto 0);
--      signal RE_Timer2                        : std_logic;
--      signal WE_Timer2                        : std_logic;
 
        signal Data_memory_addr : std_logic_vector(11 downto 0);
        signal RE_data_memory   : std_logic;
        signal WE_data_memory   : std_logic;
 
        signal RE_bank                  : std_logic;
        signal WE_bank                  : std_logic;
        signal Bank_selection   : std_logic_vector(0 to Banks_number-1);
        signal Bank_data_address        : std_logic_vector(7 downto 0);
--      signal Bank_data                        : std_logic_vector(7 downto 0);
 
 
 
begin
 
MCIPcore : MCIPopen
Generic map ( STKPTR_length => STKPTR_length,
                                  STVREN => STVREN,
                                  WDTPS => WDTPS,
                                  WDTEN => WDTEN)
Port map ( nreset             => nreset,
           clock              => clk25MHz,
                          Wdt_clock                             => Wdt_clock,
           Instruction        => Inst_bus,
                          clock_out          => clock_out,
                          nresetDevice       => mcu_nreset,
                          Q1                 => Q1,
                          Q4                 => Q4,
                          RE_ram             => RE_data_memory,
                          WE_ram             => WE_data_memory,
           Istruction_address => Prg_addr,
           Data_address       => Data_memory_addr,
           Data_Bus           => Data_bus,
           PORTA              => PORTA,
           PORTB              => PORTB,
           PORTC              => PORTC,
           PORTD              => PORTD);
--Port map ( nreset                                     => nreset,
--           mcu_nreset                 => mcu_nreset,
--                        
--           clk                                                => clk_2,
--                        Wdt_clk                               => clk_2,
--           internal_clock             => internal_clock,
--           Qi                                         => Qi,
--                        
--                        Data_addr                             => Data_addr,
--           Data_bus                           => Data_bus,
--           RE                                         => mcu_RE,
--           WE                                         => mcu_WE,
--                        
--           RE_intr_con                        => RE_intr_con,
--           WE_intr_con                        => WE_intr_con,
--                        SFR_address_intr_con => SFR_address_intr_con,
--                        
--                        Prg_addr                              => Prg_addr,
--                        Inst_bus                              => Inst_bus,
--                        
--                        enable_sleep                  => enable_sleep,
--                        WDTwake_up                    => WDTwake_up,
--           sleep_enabled              => sleep_enabled,
--                        
--                        -- Debug signals
----                      IR_register       => IR_register,
----                      Status_register   => Status_register,
----           NewStatus       => NewStatus,
----           Command_PC       => Command_PC,
--                        ----------------
--
--           INTH                                       => INTH,
--           INTL                                       => INTL,
--           GIE                                                => GIE,
--           GIEL                                       => GIEL,
--           GIEHfeedback                       => GIEHfeedback,
--           GIELfeedback                       => GIELfeedback,
--           load_INTCON                        => load_INTCON,
--           IPEN                                       => IPEN
--                        );
 
-- Data and Program memories
 
Data_Memory_Controller : Data_Memory_Banks_Controller
Port map ( RE                                           => RE_data_memory,
           WE                                           => WE_data_memory,
                          Data_address                  => Data_memory_addr,
--           DATA                                       => Data_bus,
 
           RE_bank                              => RE_bank,
           WE_bank                              => WE_bank,
           Bank_selection               => Bank_selection,
           Bank_data_address    => Bank_data_address
--           Bank_data                  => Bank_data
                          );
 
Memory_banks : for i in 0 to Banks_number-1 generate
        bank: Memory_bank
Port map ( Address => Bank_data_address,
           enable  => Bank_selection(i),
           RE      => RE_bank,
                          WE      => WE_bank,
           Q1      => Q1,
           Q4      => Q4,
           DATA    => Data_bus);
        end generate;
 
Prg_Memory_Controller : Program_Memory_Controller
Port map ( Prg_addr                     => Prg_addr,
                          Instruction           => Inst_bus,
 
                          eff_Prg_addr          => eff_Prg_addr,
                          Prg_memory_bus        => Prg_memory_bus);
 
Prg_Memory : Program_Memory
Port map ( Address => eff_Prg_addr,
           nreset  => mcu_nreset,
           Q1      => Q1,
           Instruction => Prg_memory_bus);
 
 
--CLOCKpros : process(clk, nreset)
--begin
--      if nreset = '0' then
--              clk_2 <= '0';
--      elsif clk'event and clk = '1' then
--              clk_2 <= not clk_2;
--      end if;
--end process;
 
 
 
end Behavioral;
 

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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [MCIPopen_mcu_example.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	mezzah	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 18:09:51 07/24/2015`
6			`-- Design Name:`
7			`-- Module Name: MCIPopen_mcu_example - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22
23
24			`entity MCIPopen_mcu_example is`
25			`Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length --> min = 2, max = 5`
26			`STVREN : std_logic := '1'; -- Stack Overflow/Underflow Reset Enable bit`
27
28			`WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits`
29			`WDTEN : std_logic := '0'; -- Watchdog Timer enable bit`
30
31			`Banks_number : integer := 3; -- number of banks, min = 2, max = 16`
32			`dm_TOPaddr : std_logic_vector(11 downto 0) := x"2FF";`
33
34			`IAlength : integer := 12; -- min = 2, max = 21`
35			`pm_TOPaddr : std_logic_vector(20 downto 0) := '0'&x"03FFF"`
36			`);`
37
38			`Port ( nreset : in std_logic;`
39			`clk25MHz : in std_logic;`
40			`Wdt_clock : in std_logic;`
41			`clock_out : out std_logic;`
42			`PORTA : inout std_logic_vector(7 downto 0);`
43			`PORTB : inout std_logic_vector(7 downto 0);`
44			`PORTC : inout std_logic_vector(7 downto 0);`
45			`PORTD : inout std_logic_vector(7 downto 0) );`
46			`end MCIPopen_mcu_example;`
47
48			`architecture Behavioral of MCIPopen_mcu_example is`
49
50			`component MCIPopen is`
51			`Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length -- < 6`
52			`STVREN : std_logic := '1'; -- Stack Overflow/Underflow Reset Enable bit`
53			`WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits`
54			`WDTEN : std_logic := '0'); -- Watchdog Timer enable bit`
55			`Port ( nreset : in std_logic;`
56			`clock : in std_logic;`
57			`Wdt_clock : in std_logic;`
58			`Instruction : in std_logic_vector(15 downto 0);`
59			`clock_out : out std_logic;`
60			`nresetDevice : out std_logic;`
61			`Q1 : out std_logic;`
62			`Q4 : out std_logic;`
63			`RE_ram : out std_logic;`
64			`WE_ram : out std_logic;`
65			`Istruction_address : out std_logic_vector(20 downto 0);`
66			`Data_address : out std_logic_vector(11 downto 0);`
67			`Data_Bus : inout std_logic_vector(7 downto 0);`
68			`PORTA : inout std_logic_vector(7 downto 0);`
69			`PORTB : inout std_logic_vector(7 downto 0);`
70			`PORTC : inout std_logic_vector(7 downto 0);`
71			`PORTD : inout std_logic_vector(7 downto 0) );`
72			`end component MCIPopen;`
73
74
75			`component Data_Memory_Banks_Controller is`
76			`Generic (Banks_number : integer := Banks_number; -- number of banks, min = 2, max = 16`
77			`dm_TOPaddr : std_logic_vector(11 downto 0) := dm_TOPaddr);`
78			`Port ( RE : in std_logic;`
79			`WE : in std_logic;`
80			`Data_address : in std_logic_vector(11 downto 0);`
81			`-- DATA : inout std_logic_vector(7 downto 0);`
82
83			`RE_bank : out std_logic;`
84			`WE_bank : out std_logic;`
85			`Bank_selection : out std_logic_vector(0 to Banks_number-1);`
86			`Bank_data_address : out std_logic_vector(7 downto 0)`
87			`-- Bank_data : inout std_logic_vector(7 downto 0)`
88			`);`
89			`end component Data_Memory_Banks_Controller;`
90
91			`component Memory_bank is`
92			`Port ( Address : in std_logic_vector(7 downto 0);`
93			`enable : in std_logic;`
94			`RE : in std_logic;`
95			`WE : in std_logic;`
96			`Q1 : in std_logic;`
97			`Q4 : in std_logic;`
98			`DATA : inout std_logic_vector(7 downto 0));`
99			`end component Memory_bank;`
100
101			`component Program_Memory_Controller is`
102			`Generic (IAlength : integer := IAlength; -- min = 2, max = 21`
103			`pm_TOPaddr : std_logic_vector(20 downto 0) := pm_TOPaddr);`
104			`Port ( Prg_addr : in std_logic_vector(20 downto 0);`
105			`Instruction : out std_logic_vector(15 downto 0);`
106
107			`eff_Prg_addr : out std_logic_vector(IAlength-1 downto 0);`
108			`Prg_memory_bus : in std_logic_vector(15 downto 0));`
109			`end component Program_Memory_Controller;`
110
111			`component Program_Memory is`
112			`Generic (IAlength : integer := IAlength); -- Instruction Address Length -- min = 2, max = 21`
113			`Port ( Address : in std_logic_vector(IALength-1 downto 0);`
114			`nreset : in std_logic;`
115			`Q1 : in std_logic;`
116			`Instruction : out std_logic_vector(15 downto 0));`
117			`end component Program_Memory;`
118
119			`-- signal clk_2 : std_logic;`
120			`-- signal clk_3 : std_logic_vector(1 downto 0);`
121
122			`signal mcu_nreset : std_logic;`
123			`-- signal internal_clock : std_logic;`
124			`signal Q1 : std_logic;`
125			`signal Q4 : std_logic;`
126
127			`-- signal Data_addr : std_logic_vector(11 downto 0);`
128			`signal Data_bus : std_logic_vector(7 downto 0);`
129			`-- signal mcu_RE : std_logic;`
130			`-- signal mcu_WE : std_logic;`
131
132			`-- signal RE_intr_con : std_logic;`
133			`-- signal WE_intr_con : std_logic;`
134			`-- signal SFR_address_intr_con: std_logic_vector(4 downto 0);`
135
136			`signal Prg_addr : std_logic_vector(20 downto 0);`
137			`signal Inst_bus : std_logic_vector(15 downto 0);`
138
139			`signal eff_Prg_addr : std_logic_vector(IAlength-1 downto 0);`
140			`signal Prg_memory_bus : std_logic_vector(15 downto 0);`
141
142			`-- signal enable_sleep : std_logic;`
143			`-- signal WDTwake_up : std_logic;`
144			`-- signal sleep_enabled : std_logic;`
145
146			`-- signal INTH : std_logic;`
147			`-- signal INTL : std_logic;`
148			`-- signal GIE : std_logic;`
149			`-- signal GIEL : std_logic;`
150			`-- signal GIEHfeedback : std_logic;`
151			`-- signal GIELfeedback : std_logic;`
152			`-- signal load_INTCON : std_logic;`
153			`-- signal IPEN : std_logic;`
154			`--`
155			`-- signal Interrupt : std_logic_vector(1 to Intr_Nbr);`
156			`-- signal Interrupt_ack : std_logic_vector(1 to Intr_Nbr);`
157			`--`
158			`-- signal PORTC_addr : std_logic_vector(3 downto 0);`
159			`-- signal RE_PORTC : std_logic;`
160			`-- signal WE_PORTC : std_logic;`
161			`--`
162			`-- signal PORTD_addr : std_logic_vector(3 downto 0);`
163			`-- signal RE_PORTD : std_logic;`
164			`-- signal WE_PORTD : std_logic;`
165			`--`
166			`-- signal Timer2_addr : std_logic_vector(1 downto 0);`
167			`-- signal RE_Timer2 : std_logic;`
168			`-- signal WE_Timer2 : std_logic;`
169
170			`signal Data_memory_addr : std_logic_vector(11 downto 0);`
171			`signal RE_data_memory : std_logic;`
172			`signal WE_data_memory : std_logic;`
173
174			`signal RE_bank : std_logic;`
175			`signal WE_bank : std_logic;`
176			`signal Bank_selection : std_logic_vector(0 to Banks_number-1);`
177			`signal Bank_data_address : std_logic_vector(7 downto 0);`
178			`-- signal Bank_data : std_logic_vector(7 downto 0);`
179
180
181
182			`begin`
183
184			`MCIPcore : MCIPopen`
185			`Generic map ( STKPTR_length => STKPTR_length,`
186			`STVREN => STVREN,`
187			`WDTPS => WDTPS,`
188			`WDTEN => WDTEN)`
189			`Port map ( nreset => nreset,`
190			`clock => clk25MHz,`
191			`Wdt_clock => Wdt_clock,`
192			`Instruction => Inst_bus,`
193			`clock_out => clock_out,`
194			`nresetDevice => mcu_nreset,`
195			`Q1 => Q1,`
196			`Q4 => Q4,`
197			`RE_ram => RE_data_memory,`
198			`WE_ram => WE_data_memory,`
199			`Istruction_address => Prg_addr,`
200			`Data_address => Data_memory_addr,`
201			`Data_Bus => Data_bus,`
202			`PORTA => PORTA,`
203			`PORTB => PORTB,`
204			`PORTC => PORTC,`
205			`PORTD => PORTD);`
206			`--Port map ( nreset => nreset,`
207			`-- mcu_nreset => mcu_nreset,`
208			`--`
209			`-- clk => clk_2,`
210			`-- Wdt_clk => clk_2,`
211			`-- internal_clock => internal_clock,`
212			`-- Qi => Qi,`
213			`--`
214			`-- Data_addr => Data_addr,`
215			`-- Data_bus => Data_bus,`
216			`-- RE => mcu_RE,`
217			`-- WE => mcu_WE,`
218			`--`
219			`-- RE_intr_con => RE_intr_con,`
220			`-- WE_intr_con => WE_intr_con,`
221			`-- SFR_address_intr_con => SFR_address_intr_con,`
222			`--`
223			`-- Prg_addr => Prg_addr,`
224			`-- Inst_bus => Inst_bus,`
225			`--`
226			`-- enable_sleep => enable_sleep,`
227			`-- WDTwake_up => WDTwake_up,`
228			`-- sleep_enabled => sleep_enabled,`
229			`--`
230			`-- -- Debug signals`
231			`---- IR_register => IR_register,`
232			`---- Status_register => Status_register,`
233			`---- NewStatus => NewStatus,`
234			`---- Command_PC => Command_PC,`
235			`-- ----------------`
236			`--`
237			`-- INTH => INTH,`
238			`-- INTL => INTL,`
239			`-- GIE => GIE,`
240			`-- GIEL => GIEL,`
241			`-- GIEHfeedback => GIEHfeedback,`
242			`-- GIELfeedback => GIELfeedback,`
243			`-- load_INTCON => load_INTCON,`
244			`-- IPEN => IPEN`
245			`-- );`
246
247			`-- Data and Program memories`
248
249			`Data_Memory_Controller : Data_Memory_Banks_Controller`
250			`Port map ( RE => RE_data_memory,`
251			`WE => WE_data_memory,`
252			`Data_address => Data_memory_addr,`
253			`-- DATA => Data_bus,`
254
255			`RE_bank => RE_bank,`
256			`WE_bank => WE_bank,`
257			`Bank_selection => Bank_selection,`
258			`Bank_data_address => Bank_data_address`
259			`-- Bank_data => Bank_data`
260			`);`
261
262			`Memory_banks : for i in 0 to Banks_number-1 generate`
263			`bank: Memory_bank`
264			`Port map ( Address => Bank_data_address,`
265			`enable => Bank_selection(i),`
266			`RE => RE_bank,`
267			`WE => WE_bank,`
268			`Q1 => Q1,`
269			`Q4 => Q4,`
270			`DATA => Data_bus);`
271			`end generate;`
272
273			`Prg_Memory_Controller : Program_Memory_Controller`
274			`Port map ( Prg_addr => Prg_addr,`
275			`Instruction => Inst_bus,`
276
277			`eff_Prg_addr => eff_Prg_addr,`
278			`Prg_memory_bus => Prg_memory_bus);`
279
280			`Prg_Memory : Program_Memory`
281			`Port map ( Address => eff_Prg_addr,`
282			`nreset => mcu_nreset,`
283			`Q1 => Q1,`
284			`Instruction => Prg_memory_bus);`
285
286
287			`--CLOCKpros : process(clk, nreset)`
288			`--begin`
289			`-- if nreset = '0' then`
290			`-- clk_2 <= '0';`
291			`-- elsif clk'event and clk = '1' then`
292			`-- clk_2 <= not clk_2;`
293			`-- end if;`
294			`--end process;`
295
296
297
298			`end Behavioral;`
299