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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [MCIPopen_mcu_example.vhd] - Blame information for rev 4

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----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    18:09:51 07/24/2015 
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-- Design Name: 
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-- Module Name:    MCIPopen_mcu_example - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
11
-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity MCIPopen_mcu_example is
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         Generic (      STKPTR_length   : integer := 5;         -- Stack Pointer Length --> min = 2, max = 5
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                                        STVREN                  : std_logic := '1';     -- Stack Overflow/Underflow Reset Enable bit
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                                        WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
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                                        WDTEN : std_logic := '0'; -- Watchdog Timer enable bit
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                                        Banks_number            : integer := 3; -- number of banks, min = 2, max = 16
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                                        dm_TOPaddr                      : std_logic_vector(11 downto 0) := x"2FF";
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                                        IAlength                : integer := 12; -- min = 2, max = 21
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                                        pm_TOPaddr              : std_logic_vector(20 downto 0) := '0'&x"03FFF"
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                                        );
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    Port ( nreset             : in std_logic;
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           clk25MHz           : in std_logic;
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                          Wdt_clock                             : in std_logic;
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                          clock_out          : out std_logic;
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           PORTA              : inout std_logic_vector(7 downto 0);
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           PORTB              : inout std_logic_vector(7 downto 0);
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           PORTC              : inout std_logic_vector(7 downto 0);
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           PORTD              : inout std_logic_vector(7 downto 0) );
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end MCIPopen_mcu_example;
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architecture Behavioral of MCIPopen_mcu_example is
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component MCIPopen is
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    Generic ( STKPTR_length : integer := 5;  -- Stack Pointer Length -- < 6
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                                  STVREN : std_logic := '1';    -- Stack Overflow/Underflow Reset Enable bit
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                                  WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
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                                  WDTEN : std_logic := '0'); -- Watchdog Timer enable bit
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    Port ( nreset             : in std_logic;
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           clock              : in std_logic;
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                          Wdt_clock                             : in std_logic;
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           Instruction        : in std_logic_vector(15 downto 0);
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                          clock_out          : out std_logic;
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                          nresetDevice       : out std_logic;
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                          Q1                 : out std_logic;
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                          Q4                 : out std_logic;
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                          RE_ram             : out std_logic;
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                          WE_ram             : out std_logic;
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           Istruction_address : out std_logic_vector(20 downto 0);
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           Data_address       : out std_logic_vector(11 downto 0);
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           Data_Bus           : inout std_logic_vector(7 downto 0);
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           PORTA              : inout std_logic_vector(7 downto 0);
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           PORTB              : inout std_logic_vector(7 downto 0);
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           PORTC              : inout std_logic_vector(7 downto 0);
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           PORTD              : inout std_logic_vector(7 downto 0) );
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end component MCIPopen;
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component Data_Memory_Banks_Controller is
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         Generic (Banks_number          : integer := Banks_number;      -- number of banks, min = 2, max = 16
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                                 dm_TOPaddr                     : std_logic_vector(11 downto 0) := dm_TOPaddr);
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    Port ( RE                                           : in std_logic;
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           WE                                           : in std_logic;
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                          Data_address                  : in std_logic_vector(11 downto 0);
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--           DATA                                       : inout std_logic_vector(7 downto 0);
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           RE_bank                              : out std_logic;
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           WE_bank                              : out std_logic;
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           Bank_selection               : out std_logic_vector(0 to Banks_number-1);
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           Bank_data_address    : out std_logic_vector(7 downto 0)
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--           Bank_data                  : inout std_logic_vector(7 downto 0)
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                          );
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end component Data_Memory_Banks_Controller;
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component Memory_bank is
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    Port ( Address : in std_logic_vector(7 downto 0);
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           enable  : in std_logic;
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           RE      : in std_logic;
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                          WE      : in std_logic;
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           Q1      : in std_logic;
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           Q4      : in std_logic;
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           DATA    : inout std_logic_vector(7 downto 0));
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end component Memory_bank;
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component Program_Memory_Controller is
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         Generic (IAlength              : integer := IAlength; -- min = 2, max = 21
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                                 pm_TOPaddr             : std_logic_vector(20 downto 0) := pm_TOPaddr);
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    Port ( Prg_addr                     : in std_logic_vector(20 downto 0);
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                          Instruction           : out std_logic_vector(15 downto 0);
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                          eff_Prg_addr          : out std_logic_vector(IAlength-1 downto 0);
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                          Prg_memory_bus        : in std_logic_vector(15 downto 0));
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end component Program_Memory_Controller;
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component Program_Memory is
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         Generic (IAlength              : integer := IAlength);  -- Instruction Address Length -- min = 2, max = 21
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    Port ( Address : in std_logic_vector(IALength-1 downto 0);
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           nreset  : in std_logic;
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           Q1      : in std_logic;
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           Instruction : out std_logic_vector(15 downto 0));
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end component Program_Memory;
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--      signal clk_2                            : std_logic;
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--      signal clk_3                            : std_logic_vector(1 downto 0);
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        signal mcu_nreset                       : std_logic;
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--      signal internal_clock   : std_logic;
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        signal Q1                                       : std_logic;
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        signal Q4                                       : std_logic;
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127
--      signal Data_addr                        : std_logic_vector(11 downto 0);
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        signal Data_bus                 : std_logic_vector(7 downto 0);
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--      signal mcu_RE                           : std_logic;
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--      signal mcu_WE                           : std_logic;
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--      signal RE_intr_con              : std_logic;
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--      signal WE_intr_con              : std_logic;
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--      signal SFR_address_intr_con: std_logic_vector(4 downto 0);
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        signal Prg_addr                 : std_logic_vector(20 downto 0);
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        signal Inst_bus                 : std_logic_vector(15 downto 0);
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        signal eff_Prg_addr             : std_logic_vector(IAlength-1 downto 0);
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        signal Prg_memory_bus   : std_logic_vector(15 downto 0);
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--      signal enable_sleep             : std_logic;
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--      signal WDTwake_up                       : std_logic;
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--      signal sleep_enabled            : std_logic;
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--      signal INTH                                     : std_logic;
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--      signal INTL                                     : std_logic;
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--      signal GIE                                      : std_logic;
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--      signal GIEL                                     : std_logic;
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--      signal GIEHfeedback             : std_logic;
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--      signal GIELfeedback             : std_logic;
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--      signal load_INTCON              : std_logic;
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--      signal IPEN                                     : std_logic;
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--
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--      signal Interrupt                        : std_logic_vector(1 to Intr_Nbr);
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--      signal Interrupt_ack            : std_logic_vector(1 to Intr_Nbr);
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--
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--      signal PORTC_addr                       : std_logic_vector(3 downto 0);
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--      signal RE_PORTC                 : std_logic;
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--      signal WE_PORTC                 : std_logic;
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--
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--      signal PORTD_addr                       : std_logic_vector(3 downto 0);
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--      signal RE_PORTD                 : std_logic;
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--      signal WE_PORTD                 : std_logic;
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--
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--      signal Timer2_addr              : std_logic_vector(1 downto 0);
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--      signal RE_Timer2                        : std_logic;
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--      signal WE_Timer2                        : std_logic;
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        signal Data_memory_addr : std_logic_vector(11 downto 0);
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        signal RE_data_memory   : std_logic;
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        signal WE_data_memory   : std_logic;
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        signal RE_bank                  : std_logic;
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        signal WE_bank                  : std_logic;
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        signal Bank_selection   : std_logic_vector(0 to Banks_number-1);
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        signal Bank_data_address        : std_logic_vector(7 downto 0);
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--      signal Bank_data                        : std_logic_vector(7 downto 0);
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begin
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MCIPcore : MCIPopen
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Generic map ( STKPTR_length => STKPTR_length,
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                                  STVREN => STVREN,
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                                  WDTPS => WDTPS,
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                                  WDTEN => WDTEN)
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Port map ( nreset             => nreset,
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           clock              => clk25MHz,
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                          Wdt_clock                             => Wdt_clock,
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           Instruction        => Inst_bus,
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                          clock_out          => clock_out,
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                          nresetDevice       => mcu_nreset,
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                          Q1                 => Q1,
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                          Q4                 => Q4,
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                          RE_ram             => RE_data_memory,
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                          WE_ram             => WE_data_memory,
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           Istruction_address => Prg_addr,
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           Data_address       => Data_memory_addr,
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           Data_Bus           => Data_bus,
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           PORTA              => PORTA,
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           PORTB              => PORTB,
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           PORTC              => PORTC,
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           PORTD              => PORTD);
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--Port map ( nreset                                     => nreset,
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--           mcu_nreset                 => mcu_nreset,
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--                        
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--           clk                                                => clk_2,
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--                        Wdt_clk                               => clk_2,
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--           internal_clock             => internal_clock,
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--           Qi                                         => Qi,
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--                        
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--                        Data_addr                             => Data_addr,
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--           Data_bus                           => Data_bus,
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--           RE                                         => mcu_RE,
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--           WE                                         => mcu_WE,
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--                        
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--           RE_intr_con                        => RE_intr_con,
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--           WE_intr_con                        => WE_intr_con,
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--                        SFR_address_intr_con => SFR_address_intr_con,
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--                        
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--                        Prg_addr                              => Prg_addr,
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--                        Inst_bus                              => Inst_bus,
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--                        
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--                        enable_sleep                  => enable_sleep,
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--                        WDTwake_up                    => WDTwake_up,
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--           sleep_enabled              => sleep_enabled,
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--                        
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--                        -- Debug signals
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----                      IR_register       => IR_register,
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----                      Status_register   => Status_register,
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----           NewStatus       => NewStatus,
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----           Command_PC       => Command_PC,
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--                        ----------------
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--
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--           INTH                                       => INTH,
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--           INTL                                       => INTL,
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--           GIE                                                => GIE,
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--           GIEL                                       => GIEL,
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--           GIEHfeedback                       => GIEHfeedback,
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--           GIELfeedback                       => GIELfeedback,
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--           load_INTCON                        => load_INTCON,
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--           IPEN                                       => IPEN
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--                        );
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-- Data and Program memories
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Data_Memory_Controller : Data_Memory_Banks_Controller
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Port map ( RE                                           => RE_data_memory,
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           WE                                           => WE_data_memory,
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                          Data_address                  => Data_memory_addr,
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--           DATA                                       => Data_bus,
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           RE_bank                              => RE_bank,
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           WE_bank                              => WE_bank,
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           Bank_selection               => Bank_selection,
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           Bank_data_address    => Bank_data_address
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--           Bank_data                  => Bank_data
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                          );
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Memory_banks : for i in 0 to Banks_number-1 generate
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        bank: Memory_bank
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Port map ( Address => Bank_data_address,
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           enable  => Bank_selection(i),
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           RE      => RE_bank,
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                          WE      => WE_bank,
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           Q1      => Q1,
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           Q4      => Q4,
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           DATA    => Data_bus);
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        end generate;
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Prg_Memory_Controller : Program_Memory_Controller
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Port map ( Prg_addr                     => Prg_addr,
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                          Instruction           => Inst_bus,
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                          eff_Prg_addr          => eff_Prg_addr,
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                          Prg_memory_bus        => Prg_memory_bus);
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Prg_Memory : Program_Memory
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Port map ( Address => eff_Prg_addr,
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           nreset  => mcu_nreset,
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           Q1      => Q1,
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           Instruction => Prg_memory_bus);
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--CLOCKpros : process(clk, nreset)
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--begin
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--      if nreset = '0' then
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--              clk_2 <= '0';
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--      elsif clk'event and clk = '1' then
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--              clk_2 <= not clk_2;
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--      end if;
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--end process;
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end Behavioral;
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