Subversion Repositories mcip_open

----------------------------------------------------------------------------------

-- Company:        Ferhat Abbas University - Algeria

-- Engineer:       Ibrahim MEZZAH

-- 

-- Create Date:    15:58:29 06/17/2013 

-- Design Name: 

-- Module Name:    Memory_bank - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Memory_bank is

    Port ( Address : in std_logic_vector(7 downto 0);

           enable  : in std_logic;

           RE      : in std_logic;

                          WE      : in std_logic;

           Q1      : in std_logic;

           Q4      : in std_logic;

           DATA    : inout std_logic_vector(7 downto 0));

end Memory_bank;

architecture Behavioral of Memory_bank is

        type Ram_Table is array(0 to 255) of std_logic_vector(7 downto 0);

        signal Bank : Ram_Table := (others => X"00");

        signal data_read : std_logic_vector(7 downto 0);

        signal data_write : std_logic_vector(7 downto 0);

begin

        data_read <= Bank(CONV_INTEGER(Address));

        data_write <= DATA;

        DATA <= data_read         when enable = '1' and RE = '1' and Q1 = '1' else (others => 'Z');

        process

        begin

          wait until rising_edge(Q4);

                 if enable = '1' and WE = '1' then

                         Bank(CONV_INTEGER(Address)) <= data_write;

                 end if;

        end process;

end Behavioral;