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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Operation_Unit.vhd] - Blame information for rev 4

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--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    23:44:46 05/28/05
-- Design Name:    Process unit
-- Module Name:    Calcul_Unit - Calcul
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:  This process unit includes 8-bits ALU,
--                                               hard multiplier, and several 8-bits work registers
--                                               WREG, WREGs, PRODL, PRODH, FREG.
-- Revision:             07/07/2008
-- Revision  2.2 - Add description
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Operation_Unit is
    Port ( nreset        : in std_logic;
           Q             : in std_logic_vector(1 to 4);
                          CommandVector : in std_logic_vector(13 downto 0);
           CommandStatus : in std_logic_vector(4 downto 0);
           OldStatus     : in std_logic_vector(4 downto 0);
           R_W           : in std_logic_vector(1 downto 0);
           BitOp         : in std_logic_vector(2 downto 0);
                          call_return   : in std_logic_vector(1 downto 0);
                          Address_Latch : in std_logic_vector(1 downto 0);
                          BitOp_enable  : in std_logic;
                          WREG_write    : in std_logic;
                          MUL_enable    : in std_logic;
                          Read_result   : in std_logic;
                          Load_FREG     : in std_logic;
           DATA          : inout std_logic_vector(7 downto 0);
           NewStatus     : out std_logic_vector(4 downto 0);
                          SetResponse   : out std_logic_vector(1 downto 0) );
end Operation_Unit;
 
architecture Behavioral of Operation_Unit is
 
component ALU
    Port ( CommandVector : in std_logic_vector(13 downto 0);
                          CommandStatus : in std_logic_vector(4 downto 0);
                          OldStatus     : in std_logic_vector(4 downto 0);
                          a             : in std_logic_vector(7 downto 0);
                          b             : in std_logic_vector(7 downto 0);
                          s             : out std_logic_vector(7 downto 0);
                          NewStatus     : out std_logic_vector(4 downto 0);
                          SetResponse   : out std_logic_vector(1 downto 0) );
end component ALU;
 
component Multiplier
    Port ( Q          : in std_logic;
                          MUL_enable : in std_logic;
                          a          : in std_logic_vector(7 downto 0);
                          b          : in std_logic_vector(7 downto 0);
                          PROD       : out std_logic_vector(15 downto 0) );
end component Multiplier;
 
        signal WREG  : std_logic_vector(7 downto 0);
        signal PRODL : std_logic_vector(7 downto 0);
        signal PRODH : std_logic_vector(7 downto 0);
        signal FREG  : std_logic_vector(7 downto 0);
        signal WREGs : std_logic_vector(7 downto 0);
 
        signal DATA_read  : std_logic_vector(7 downto 0);
        signal DATA_write : std_logic_vector(7 downto 0);
 
        signal a_ALU  : std_logic_vector(7 downto 0);
        signal b_ALU  : std_logic_vector(7 downto 0);
        signal result : std_logic_vector(7 downto 0);
 
        signal PROD : std_logic_vector(15 downto 0);
 
   alias read_D  : std_logic is R_W(1);
   alias write_D : std_logic is R_W(0);
 
        alias Q1 : std_logic is Q(1);
        alias Q2 : std_logic is Q(2);
        alias Q3 : std_logic is Q(3);
        alias Q4 : std_logic is Q(4);
 
begin
 
ALUnit : ALU
port map (  CommandVector => CommandVector,
                                CommandStatus => CommandStatus,
                                OldStatus     => OldStatus,
                                a             => a_alu,
                                b             => b_alu,
                                s             => result,
                                NewStatus     => NewStatus,
                                SetResponse   => SetResponse );
 
MUL : Multiplier
Port map ( Q          => Q3,
                          MUL_enable => MUL_enable,
                          a          => FREG,
                          b          => WREG,
                          PROD       => PROD );
 
        a_alu <= FREG;
        b_alu <= WREG(7 downto 3) & BitOp                                when BitOp_enable = '1' else
                                WREG;
 
        DATA_read <= PRODL                                                                       when Address_Latch(0) = '1' else
                                         PRODH                                                                   when Address_Latch(1) = '1' else
                                         WREG;
 
        DATA_write <= DATA;
 
Latchs_p :  process (nreset, Q1, Q2, Q3, Q4, write_D, DATA_write, MUL_enable,
                                                        call_return, Address_Latch, PROD, WREGs, WREG, Load_FREG)
  begin
                 if nreset = '0' then
                                 WREG  <= (others => '0');
                                 PRODH <= (others => '0');
                                 PRODL <= (others => '0');
                                 FREG  <= (others => '0');
                                 WREGs <= (others => '0');
                 else
                  if (Q4'event and Q4 = '1') then
                        if MUL_enable = '1' then
                                PRODL <= PROD(7 downto 0);
                                PRODH <= PROD(15 downto 8);
                        else
                                if write_D = '1' then
                                 if Address_Latch(1) = '1' then
                                         PRODH <= DATA_write;
                                 elsif Address_Latch(0) = '1' then
                                         PRODL <= DATA_write;
                                 end if;
                                end if;
                        end if;
                        if WREG_write = '1' or
                                (write_D = '1' and Address_Latch = "00") then
                                WREG <= DATA_write;
                        elsif call_return(1) = '1' then
                                if call_return(0) = '0' then
                                        WREGs <= WREG;                                          -- call
                                else
                                        WREG <= WREGs;                                          -- return
                                end if;
                        end if;
                  end if;
                  if ((Q2'event and Q2 = '1') and Load_FREG = '1') then
                         FREG <= DATA_write;
                  end if;
                 end if;
        end process;
 
         DATA <= DATA_read                                              when (Q1 = '1' and read_D = '1') else
                                result                                                  when (Q3 = '1' and Read_result = '1') else
                                (others => 'Z');
 
end Behavioral;

Line No.	Rev	Author	Line
1	4	mezzah	`--------------------------------------------------------------------------------`
2			`-- Company: Ferhat Abbas University - Algeria`
3			`-- Engineer: Ibrahim MEZZAH`
4			`-- Progect Supervisor: Dr H. Chemali`
5			`-- Create Date: 23:44:46 05/28/05`
6			`-- Design Name: Process unit`
7			`-- Module Name: Calcul_Unit - Calcul`
8			`-- Project Name: Microcontroller IP (MCIP)`
9			`-- Target Device: xc3s500e-4fg320`
10			`-- Tool versions: Xilinx ISE 9.1.03i`
11			`-- Description: This process unit includes 8-bits ALU,`
12			`-- hard multiplier, and several 8-bits work registers`
13			`-- WREG, WREGs, PRODL, PRODH, FREG.`
14			`-- Revision: 07/07/2008`
15			`-- Revision 2.2 - Add description`
16			`--------------------------------------------------------------------------------`
17			`library IEEE;`
18			`use IEEE.STD_LOGIC_1164.ALL;`
19
20			`entity Operation_Unit is`
21			`Port ( nreset : in std_logic;`
22			`Q : in std_logic_vector(1 to 4);`
23			`CommandVector : in std_logic_vector(13 downto 0);`
24			`CommandStatus : in std_logic_vector(4 downto 0);`
25			`OldStatus : in std_logic_vector(4 downto 0);`
26			`R_W : in std_logic_vector(1 downto 0);`
27			`BitOp : in std_logic_vector(2 downto 0);`
28			`call_return : in std_logic_vector(1 downto 0);`
29			`Address_Latch : in std_logic_vector(1 downto 0);`
30			`BitOp_enable : in std_logic;`
31			`WREG_write : in std_logic;`
32			`MUL_enable : in std_logic;`
33			`Read_result : in std_logic;`
34			`Load_FREG : in std_logic;`
35			`DATA : inout std_logic_vector(7 downto 0);`
36			`NewStatus : out std_logic_vector(4 downto 0);`
37			`SetResponse : out std_logic_vector(1 downto 0) );`
38			`end Operation_Unit;`
39
40			`architecture Behavioral of Operation_Unit is`
41
42			`component ALU`
43			`Port ( CommandVector : in std_logic_vector(13 downto 0);`
44			`CommandStatus : in std_logic_vector(4 downto 0);`
45			`OldStatus : in std_logic_vector(4 downto 0);`
46			`a : in std_logic_vector(7 downto 0);`
47			`b : in std_logic_vector(7 downto 0);`
48			`s : out std_logic_vector(7 downto 0);`
49			`NewStatus : out std_logic_vector(4 downto 0);`
50			`SetResponse : out std_logic_vector(1 downto 0) );`
51			`end component ALU;`
52
53			`component Multiplier`
54			`Port ( Q : in std_logic;`
55			`MUL_enable : in std_logic;`
56			`a : in std_logic_vector(7 downto 0);`
57			`b : in std_logic_vector(7 downto 0);`
58			`PROD : out std_logic_vector(15 downto 0) );`
59			`end component Multiplier;`
60
61			`signal WREG : std_logic_vector(7 downto 0);`
62			`signal PRODL : std_logic_vector(7 downto 0);`
63			`signal PRODH : std_logic_vector(7 downto 0);`
64			`signal FREG : std_logic_vector(7 downto 0);`
65			`signal WREGs : std_logic_vector(7 downto 0);`
66
67			`signal DATA_read : std_logic_vector(7 downto 0);`
68			`signal DATA_write : std_logic_vector(7 downto 0);`
69
70			`signal a_ALU : std_logic_vector(7 downto 0);`
71			`signal b_ALU : std_logic_vector(7 downto 0);`
72			`signal result : std_logic_vector(7 downto 0);`
73
74			`signal PROD : std_logic_vector(15 downto 0);`
75
76			`alias read_D : std_logic is R_W(1);`
77			`alias write_D : std_logic is R_W(0);`
78
79			`alias Q1 : std_logic is Q(1);`
80			`alias Q2 : std_logic is Q(2);`
81			`alias Q3 : std_logic is Q(3);`
82			`alias Q4 : std_logic is Q(4);`
83
84			`begin`
85
86			`ALUnit : ALU`
87			`port map ( CommandVector => CommandVector,`
88			`CommandStatus => CommandStatus,`
89			`OldStatus => OldStatus,`
90			`a => a_alu,`
91			`b => b_alu,`
92			`s => result,`
93			`NewStatus => NewStatus,`
94			`SetResponse => SetResponse );`
95
96			`MUL : Multiplier`
97			`Port map ( Q => Q3,`
98			`MUL_enable => MUL_enable,`
99			`a => FREG,`
100			`b => WREG,`
101			`PROD => PROD );`
102
103			`a_alu <= FREG;`
104			`b_alu <= WREG(7 downto 3) & BitOp when BitOp_enable = '1' else`
105			`WREG;`
106
107			`DATA_read <= PRODL when Address_Latch(0) = '1' else`
108			`PRODH when Address_Latch(1) = '1' else`
109			`WREG;`
110
111			`DATA_write <= DATA;`
112
113			`Latchs_p : process (nreset, Q1, Q2, Q3, Q4, write_D, DATA_write, MUL_enable,`
114			`call_return, Address_Latch, PROD, WREGs, WREG, Load_FREG)`
115			`begin`
116			`if nreset = '0' then`
117			`WREG <= (others => '0');`
118			`PRODH <= (others => '0');`
119			`PRODL <= (others => '0');`
120			`FREG <= (others => '0');`
121			`WREGs <= (others => '0');`
122			`else`
123			`if (Q4'event and Q4 = '1') then`
124			`if MUL_enable = '1' then`
125			`PRODL <= PROD(7 downto 0);`
126			`PRODH <= PROD(15 downto 8);`
127			`else`
128			`if write_D = '1' then`
129			`if Address_Latch(1) = '1' then`
130			`PRODH <= DATA_write;`
131			`elsif Address_Latch(0) = '1' then`
132			`PRODL <= DATA_write;`
133			`end if;`
134			`end if;`
135			`end if;`
136			`if WREG_write = '1' or`
137			`(write_D = '1' and Address_Latch = "00") then`
138			`WREG <= DATA_write;`
139			`elsif call_return(1) = '1' then`
140			`if call_return(0) = '0' then`
141			`WREGs <= WREG; -- call`
142			`else`
143			`WREG <= WREGs; -- return`
144			`end if;`
145			`end if;`
146			`end if;`
147			`if ((Q2'event and Q2 = '1') and Load_FREG = '1') then`
148			`FREG <= DATA_write;`
149			`end if;`
150			`end if;`
151			`end process;`
152
153			`DATA <= DATA_read when (Q1 = '1' and read_D = '1') else`
154			`result when (Q3 = '1' and Read_result = '1') else`
155			`(others => 'Z');`
156
157			`end Behavioral;`

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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Operation_Unit.vhd] - Blame information for rev 4