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--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    02:10:11 05/21/01
-- Design Name:    Phase Lock Loop
-- Module Name:    PLL - Behavioral
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:    The PLL divide the clock input by four. It provides an
--                 instruction cycle that is the same frequency 
--                 as the external clock frequency. Four non-overlapping 
--                 quadrature clocks, namely Q1, Q2, Q3 and Q4 are generated.
-- Revision:             07/06/2008
-- Revision 3
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity PLL is
    Port ( clock             : in std_logic;
           nreset            : in std_logic;
           IDLEN                                  : in std_logic;
           Sleep_mode_enable : in std_logic;
           Q1                : out std_logic;
           Q2                : out std_logic;
           Q3                : out std_logic;
           Q4                : out std_logic;
           internal_clock         : out std_logic);  -- MCU clock/4
end PLL;
 
architecture Behavioral of PLL is
 
        signal Q : std_logic_vector(1 to 4);
        signal Syc : std_logic_vector(1 downto 0);
        signal Idle_Syc : std_logic;
        signal Idle : std_logic;
 
        signal clock_div4 : std_logic;
 
        signal nresetQ1 : std_logic;
        signal nresetQ3 : std_logic;
 
begin
 
          nresetQ1 <= '0'                                                 when nreset = '0' or Q(2) = '1' else
                                          '1';
          nresetQ3 <= '0'                                                 when nreset = '0' or Q(4) = '1' else
                                          '1';
          Idle    <= '1'                                                 when Sleep_mode_enable = '1' and Idle_Syc = '1' else
                                          '0';
 
          Q1 <= Q(1);
          Q2 <= Q(2);
          Q3 <= Q(3);
          Q4 <= Q(4);
 
          internal_clock <= clock_div4;
 
        Sychronise : process(nreset, clock, Idle, IDLEN, Syc)
        begin
                if nreset = '0' then
                        Syc <= "10";
                else
                        if clock'event and clock = '1' then
                                case Syc is
                                        when "10" =>
                                                if Idle = '1' and IDLEN = '0' then
                                                        Syc <= "10";
                                                else
                                                        Syc <= "00";
                                                end if;
                                        when "00" =>
                                                Syc <= "01";
                                        when "01" =>
                                                Syc <= "11";
                                        when others =>
                                                Syc <= "10";
                                end case;
                        else
                                Syc <= Syc;
                        end if;
                end if;
        end process;
 
        Out_clock : process(nreset, clock, Idle, IDLEN, Syc)
        begin
                if nreset = '0' then
                        clock_div4 <= '0';
                else
                        if clock'event and clock = '1' then
                                case Syc is
                                        when "10" =>
                                                if Idle = '1' and IDLEN = '0' then
                                                        clock_div4 <= clock_div4;
                                                else
                                                        clock_div4 <= '0';
                                                end if;
                                        when "00" =>
                                                clock_div4 <= '0';
                                        when "01" =>
                                                clock_div4 <= '1';
                                        when others =>
                                                clock_div4 <= '1';
                                end case;
                        else
                                clock_div4 <= clock_div4;
                        end if;
                end if;
        end process;
 
        Q1_p : process(nresetQ1, clock, Idle, Syc)
        begin
                if nresetQ1 = '0' then
                        Q(1) <= '0';
                else
                        if clock'event and clock = '1' then
                                if Syc = "10" then
                                        if Idle = '0' then
                                                Q(1) <= '1';
                                        else
                                                Q(1) <= Q(1);
                                        end if;
                                else
                                        Q(1) <= Q(1);
                                end if;
                        else
                                Q(1) <= Q(1);
                        end if;
                end if;
        end process;
 
        Q2_p : process(nreset, clock, Idle_Syc, Syc)
        begin
                if nreset = '0' then
                        Q(2) <= '0';
                else
                        if clock'event and clock = '1' then
                                if Syc = "00" then
                                        if Idle_Syc = '0' then
                                                Q(2) <= '1';
                                        else
                                                Q(2) <= '0';
                                        end if;
                                else
                                        Q(2) <= '0';
                                end if;
                        else
                                Q(2) <= Q(2);
                        end if;
                end if;
        end process;
 
        Q3_p : process(nresetQ3, clock, Idle_Syc, Syc)
        begin
                if nresetQ3 = '0' then
                        Q(3) <= '0';
                else
                        if clock'event and clock = '1' then
                                if Syc = "01" then
                                        if Idle_Syc = '0' then
                                                Q(3) <= '1';
                                        else
                                                Q(3) <= Q(3);
                                        end if;
                                else
                                        Q(3) <= Q(3);
                                end if;
                        else
                                Q(3) <= Q(3);
                        end if;
                end if;
        end process;
 
        Q4_p : process(nreset, clock, Idle_Syc, Syc)
        begin
                if nreset = '0' then
                        Q(4) <= '0';
                else
                        if clock'event and clock = '1' then
                                if Syc = "11" then
                                        if Idle_Syc = '0' then
                                                Q(4) <= '1';
                                        else
                                                Q(4) <= Q(4);
                                        end if;
                                elsif Syc = "10" then
                                        if Idle = '0' then
                                                Q(4) <= '0';
                                        else
                                                Q(4) <= Q(4);
                                        end if;
                                else
                                        Q(4) <= Q(4);
                                end if;
                        else
                                Q(4) <= Q(4);
                        end if;
                end if;
        end process;
 
        Idel_state : process(nreset, Q(1), Q(4), Sleep_mode_enable)
        begin
                if nreset = '0' or Q(1) = '1' then
                        Idle_Syc <= '0';
                else
                        if Q(4)'event and Q(4) = '1' then
                                Idle_Syc <= Sleep_mode_enable;
                        else
                                Idle_Syc <= Idle_Syc;
                        end if;
                end if;
        end process;
 
 
end Behavioral;

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Subversion Repositories mcip_open

[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [PLL.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	mezzah	`--------------------------------------------------------------------------------`
2			`-- Company: Ferhat Abbas University - Algeria`
3			`-- Engineer: Ibrahim MEZZAH`
4			`-- Progect Supervisor: Dr H. Chemali`
5			`-- Create Date: 02:10:11 05/21/01`
6			`-- Design Name: Phase Lock Loop`
7			`-- Module Name: PLL - Behavioral`
8			`-- Project Name: Microcontroller IP (MCIP)`
9			`-- Target Device: xc3s500e-4fg320`
10			`-- Tool versions: Xilinx ISE 9.1.03i`
11			`-- Description: The PLL divide the clock input by four. It provides an`
12			`-- instruction cycle that is the same frequency`
13			`-- as the external clock frequency. Four non-overlapping`
14			`-- quadrature clocks, namely Q1, Q2, Q3 and Q4 are generated.`
15			`-- Revision: 07/06/2008`
16			`-- Revision 3`
17			`--------------------------------------------------------------------------------`
18			`library IEEE;`
19			`use IEEE.STD_LOGIC_1164.ALL;`
20			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
21
22			`entity PLL is`
23			`Port ( clock : in std_logic;`
24			`nreset : in std_logic;`
25			`IDLEN : in std_logic;`
26			`Sleep_mode_enable : in std_logic;`
27			`Q1 : out std_logic;`
28			`Q2 : out std_logic;`
29			`Q3 : out std_logic;`
30			`Q4 : out std_logic;`
31			`internal_clock : out std_logic); -- MCU clock/4`
32			`end PLL;`
33
34			`architecture Behavioral of PLL is`
35
36			`signal Q : std_logic_vector(1 to 4);`
37			`signal Syc : std_logic_vector(1 downto 0);`
38			`signal Idle_Syc : std_logic;`
39			`signal Idle : std_logic;`
40
41			`signal clock_div4 : std_logic;`
42
43			`signal nresetQ1 : std_logic;`
44			`signal nresetQ3 : std_logic;`
45
46			`begin`
47
48			`nresetQ1 <= '0' when nreset = '0' or Q(2) = '1' else`
49			`'1';`
50			`nresetQ3 <= '0' when nreset = '0' or Q(4) = '1' else`
51			`'1';`
52			`Idle <= '1' when Sleep_mode_enable = '1' and Idle_Syc = '1' else`
53			`'0';`
54
55			`Q1 <= Q(1);`
56			`Q2 <= Q(2);`
57			`Q3 <= Q(3);`
58			`Q4 <= Q(4);`
59
60			`internal_clock <= clock_div4;`
61
62			`Sychronise : process(nreset, clock, Idle, IDLEN, Syc)`
63			`begin`
64			`if nreset = '0' then`
65			`Syc <= "10";`
66			`else`
67			`if clock'event and clock = '1' then`
68			`case Syc is`
69			`when "10" =>`
70			`if Idle = '1' and IDLEN = '0' then`
71			`Syc <= "10";`
72			`else`
73			`Syc <= "00";`
74			`end if;`
75			`when "00" =>`
76			`Syc <= "01";`
77			`when "01" =>`
78			`Syc <= "11";`
79			`when others =>`
80			`Syc <= "10";`
81			`end case;`
82			`else`
83			`Syc <= Syc;`
84			`end if;`
85			`end if;`
86			`end process;`
87
88			`Out_clock : process(nreset, clock, Idle, IDLEN, Syc)`
89			`begin`
90			`if nreset = '0' then`
91			`clock_div4 <= '0';`
92			`else`
93			`if clock'event and clock = '1' then`
94			`case Syc is`
95			`when "10" =>`
96			`if Idle = '1' and IDLEN = '0' then`
97			`clock_div4 <= clock_div4;`
98			`else`
99			`clock_div4 <= '0';`
100			`end if;`
101			`when "00" =>`
102			`clock_div4 <= '0';`
103			`when "01" =>`
104			`clock_div4 <= '1';`
105			`when others =>`
106			`clock_div4 <= '1';`
107			`end case;`
108			`else`
109			`clock_div4 <= clock_div4;`
110			`end if;`
111			`end if;`
112			`end process;`
113
114			`Q1_p : process(nresetQ1, clock, Idle, Syc)`
115			`begin`
116			`if nresetQ1 = '0' then`
117			`Q(1) <= '0';`
118			`else`
119			`if clock'event and clock = '1' then`
120			`if Syc = "10" then`
121			`if Idle = '0' then`
122			`Q(1) <= '1';`
123			`else`
124			`Q(1) <= Q(1);`
125			`end if;`
126			`else`
127			`Q(1) <= Q(1);`
128			`end if;`
129			`else`
130			`Q(1) <= Q(1);`
131			`end if;`
132			`end if;`
133			`end process;`
134
135			`Q2_p : process(nreset, clock, Idle_Syc, Syc)`
136			`begin`
137			`if nreset = '0' then`
138			`Q(2) <= '0';`
139			`else`
140			`if clock'event and clock = '1' then`
141			`if Syc = "00" then`
142			`if Idle_Syc = '0' then`
143			`Q(2) <= '1';`
144			`else`
145			`Q(2) <= '0';`
146			`end if;`
147			`else`
148			`Q(2) <= '0';`
149			`end if;`
150			`else`
151			`Q(2) <= Q(2);`
152			`end if;`
153			`end if;`
154			`end process;`
155
156			`Q3_p : process(nresetQ3, clock, Idle_Syc, Syc)`
157			`begin`
158			`if nresetQ3 = '0' then`
159			`Q(3) <= '0';`
160			`else`
161			`if clock'event and clock = '1' then`
162			`if Syc = "01" then`
163			`if Idle_Syc = '0' then`
164			`Q(3) <= '1';`
165			`else`
166			`Q(3) <= Q(3);`
167			`end if;`
168			`else`
169			`Q(3) <= Q(3);`
170			`end if;`
171			`else`
172			`Q(3) <= Q(3);`
173			`end if;`
174			`end if;`
175			`end process;`
176
177			`Q4_p : process(nreset, clock, Idle_Syc, Syc)`
178			`begin`
179			`if nreset = '0' then`
180			`Q(4) <= '0';`
181			`else`
182			`if clock'event and clock = '1' then`
183			`if Syc = "11" then`
184			`if Idle_Syc = '0' then`
185			`Q(4) <= '1';`
186			`else`
187			`Q(4) <= Q(4);`
188			`end if;`
189			`elsif Syc = "10" then`
190			`if Idle = '0' then`
191			`Q(4) <= '0';`
192			`else`
193			`Q(4) <= Q(4);`
194			`end if;`
195			`else`
196			`Q(4) <= Q(4);`
197			`end if;`
198			`else`
199			`Q(4) <= Q(4);`
200			`end if;`
201			`end if;`
202			`end process;`
203
204			`Idel_state : process(nreset, Q(1), Q(4), Sleep_mode_enable)`
205			`begin`
206			`if nreset = '0' or Q(1) = '1' then`
207			`Idle_Syc <= '0';`
208			`else`
209			`if Q(4)'event and Q(4) = '1' then`
210			`Idle_Syc <= Sleep_mode_enable;`
211			`else`
212			`Idle_Syc <= Idle_Syc;`
213			`end if;`
214			`end if;`
215			`end process;`
216
217
218			`end Behavioral;`