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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [PORTs.vhd] - Blame information for rev 4

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--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    14:36:31 05/24/05
-- Design Name:    In/Out Ports
-- Module Name:    Ports - InOutPorts
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:  Simple peripherals: 4 General purpose I/O configurable
--                                               ports --> PORTA, PORTB, PORTC and PORTD.
--                                               PORTB includes 3 External Interrupts:
-- Revision:             07/06/2008
-- Revision  2 - Add description
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity PORTs is
    Port ( nreset        : in std_logic;
           Q1            : in std_logic;
           Q4            : in std_logic;
                          RE            : in std_logic;
                          WE            : in std_logic;
           SFRs_Address  : in std_logic_vector(3 downto 0); -- data_addr(4&3&1&0)
           DATA          : inout std_logic_vector(7 downto 0);
           PORTA         : inout std_logic_vector(7 downto 0);
           PORTB         : inout std_logic_vector(7 downto 0);
           PORTC         : inout std_logic_vector(7 downto 0);
           PORTD         : inout std_logic_vector(7 downto 0));
end PORTs;
 
architecture Behavioral of PORTs is
 
  signal data_read : std_logic_vector(7 downto 0);
 
  signal TRISA : std_logic_vector(7 downto 0);
  signal TRISB : std_logic_vector(7 downto 0);
  signal TRISC : std_logic_vector(7 downto 0);
  signal TRISD : std_logic_vector(7 downto 0);
 
  signal LATA : std_logic_vector(7 downto 0);
  signal LATB : std_logic_vector(7 downto 0);
  signal LATC : std_logic_vector(7 downto 0);
  signal LATD : std_logic_vector(7 downto 0);
 
begin
 
-- SFRs write operation ---------------------------------
 
Write_pros : process( nreset, Q4, WE, SFRs_Address, DATA)
                begin
                if nreset = '0' then
                                        LATA  <= (others => '0');
                                        LATB  <= (others => '0');
                                        LATC  <= (others => '0');
                                        LATD  <= (others => '0');
                                        TRISA <= (others => '1');
                                        TRISB <= (others => '1');
                                        TRISC <= (others => '1');
                                        TRISD <= (others => '1');
                elsif Q4'event and Q4 = '1' then
                         if WE = '1' then
                                case SFRs_Address is                              -- SFR address
                                  when "1010" => TRISA <= DATA; -- F92
                                  when "1011" => TRISB <= DATA; -- F93
                                  when "1000" => TRISC <= DATA; -- F94
                                  when "1001" => TRISD <= DATA; -- F95
                                  when "0101" =>  LATA <= DATA; -- F89
                                  when "0110" =>  LATB <= DATA; -- F8A
                                  when "0111" =>  LATC <= DATA; -- F8B
                                  when "0100" =>  LATD <= DATA; -- F8C
                                  when "0000" =>  LATA <= DATA; -- F80
                                  when "0001" =>  LATB <= DATA; -- F81
                                  when "0010" =>  LATC <= DATA; -- F82
                                  when "0011" =>  LATD <= DATA; -- F83
                                  when others =>  null;
                                end case;
                         end if;
                end if;
         end process;
 
 
-- SFRs read operation ----------------------------------------------
 
        data_read <= TRISA                                        when SFRs_Address = "1010" else
                                         TRISB                                    when SFRs_Address = "1011" else
                                         TRISC                                    when SFRs_Address = "1000" else
                                         TRISD                                    when SFRs_Address = "1001" else
                                         LATA                                             when SFRs_Address = "0101" else
                                         LATB                                             when SFRs_Address = "0110" else
                                         LATC                                             when SFRs_Address = "0111" else
                                         LATD                                             when SFRs_Address = "0100" else
                                         PORTA                                    when SFRs_Address = "0000" else
                                         PORTB                                    when SFRs_Address = "0001" else
                                         PORTC                                    when SFRs_Address = "0010" else
                                         PORTD;                                 --when SFRs_Address = "0011"
 
        DATA <= data_read                                               when (Q1 = '1' and RE = '1') else
                          (others => 'Z');
 
 
-- IO PORTs assignements ---------------------------------
 
  PORA : process(TRISA, LATA)
                        begin
                          for i in 0 to 7 loop
                                  if TRISA(i) = '0' then
                                          PORTA(i) <= LATA(i);
                                  else
                                          PORTA(i) <= 'Z';
                                  end if;
                          end loop;
                end process;
 
  PORB : process(TRISB, LATB)
                        begin
                          for i in 0 to 7 loop
                                  if TRISB(i) = '0' then
                                          PORTB(i) <= LATB(i);
                                  else
                                          PORTB(i) <= 'Z';
                                  end if;
                          end loop;
                end process;
 
  PORC : process(TRISC, LATC)
                        begin
                          for i in 0 to 7 loop
                                  if TRISC(i) = '0' then
                                          PORTC(i) <= LATC(i);
                                  else
                                          PORTC(i) <= 'Z';
                                  end if;
                          end loop;
                end process;
 
  PORD : process(TRISD, LATD)
                        begin
                          for i in 0 to 7 loop
                                  if TRISD(i) = '0' then
                                          PORTD(i) <= LATD(i);
                                  else
                                          PORTD(i) <= 'Z';
                                  end if;
                          end loop;
                end process;
 
 
end Behavioral;

Line No.	Rev	Author	Line
1	4	mezzah	`--------------------------------------------------------------------------------`
2			`-- Company: Ferhat Abbas University - Algeria`
3			`-- Engineer: Ibrahim MEZZAH`
4			`-- Progect Supervisor: Dr H. Chemali`
5			`-- Create Date: 14:36:31 05/24/05`
6			`-- Design Name: In/Out Ports`
7			`-- Module Name: Ports - InOutPorts`
8			`-- Project Name: Microcontroller IP (MCIP)`
9			`-- Target Device: xc3s500e-4fg320`
10			`-- Tool versions: Xilinx ISE 9.1.03i`
11			`-- Description: Simple peripherals: 4 General purpose I/O configurable`
12			`-- ports --> PORTA, PORTB, PORTC and PORTD.`
13			`-- PORTB includes 3 External Interrupts:`
14			`-- Revision: 07/06/2008`
15			`-- Revision 2 - Add description`
16			`--------------------------------------------------------------------------------`
17			`library IEEE;`
18			`use IEEE.STD_LOGIC_1164.ALL;`
19
20			`entity PORTs is`
21			`Port ( nreset : in std_logic;`
22			`Q1 : in std_logic;`
23			`Q4 : in std_logic;`
24			`RE : in std_logic;`
25			`WE : in std_logic;`
26			`SFRs_Address : in std_logic_vector(3 downto 0); -- data_addr(4&3&1&0)`
27			`DATA : inout std_logic_vector(7 downto 0);`
28			`PORTA : inout std_logic_vector(7 downto 0);`
29			`PORTB : inout std_logic_vector(7 downto 0);`
30			`PORTC : inout std_logic_vector(7 downto 0);`
31			`PORTD : inout std_logic_vector(7 downto 0));`
32			`end PORTs;`
33
34			`architecture Behavioral of PORTs is`
35
36			`signal data_read : std_logic_vector(7 downto 0);`
37
38			`signal TRISA : std_logic_vector(7 downto 0);`
39			`signal TRISB : std_logic_vector(7 downto 0);`
40			`signal TRISC : std_logic_vector(7 downto 0);`
41			`signal TRISD : std_logic_vector(7 downto 0);`
42
43			`signal LATA : std_logic_vector(7 downto 0);`
44			`signal LATB : std_logic_vector(7 downto 0);`
45			`signal LATC : std_logic_vector(7 downto 0);`
46			`signal LATD : std_logic_vector(7 downto 0);`
47
48			`begin`
49
50			`-- SFRs write operation ---------------------------------`
51
52			`Write_pros : process( nreset, Q4, WE, SFRs_Address, DATA)`
53			`begin`
54			`if nreset = '0' then`
55			`LATA <= (others => '0');`
56			`LATB <= (others => '0');`
57			`LATC <= (others => '0');`
58			`LATD <= (others => '0');`
59			`TRISA <= (others => '1');`
60			`TRISB <= (others => '1');`
61			`TRISC <= (others => '1');`
62			`TRISD <= (others => '1');`
63			`elsif Q4'event and Q4 = '1' then`
64			`if WE = '1' then`
65			`case SFRs_Address is -- SFR address`
66			`when "1010" => TRISA <= DATA; -- F92`
67			`when "1011" => TRISB <= DATA; -- F93`
68			`when "1000" => TRISC <= DATA; -- F94`
69			`when "1001" => TRISD <= DATA; -- F95`
70			`when "0101" => LATA <= DATA; -- F89`
71			`when "0110" => LATB <= DATA; -- F8A`
72			`when "0111" => LATC <= DATA; -- F8B`
73			`when "0100" => LATD <= DATA; -- F8C`
74			`when "0000" => LATA <= DATA; -- F80`
75			`when "0001" => LATB <= DATA; -- F81`
76			`when "0010" => LATC <= DATA; -- F82`
77			`when "0011" => LATD <= DATA; -- F83`
78			`when others => null;`
79			`end case;`
80			`end if;`
81			`end if;`
82			`end process;`
83
84
85			`-- SFRs read operation ----------------------------------------------`
86
87			`data_read <= TRISA when SFRs_Address = "1010" else`
88			`TRISB when SFRs_Address = "1011" else`
89			`TRISC when SFRs_Address = "1000" else`
90			`TRISD when SFRs_Address = "1001" else`
91			`LATA when SFRs_Address = "0101" else`
92			`LATB when SFRs_Address = "0110" else`
93			`LATC when SFRs_Address = "0111" else`
94			`LATD when SFRs_Address = "0100" else`
95			`PORTA when SFRs_Address = "0000" else`
96			`PORTB when SFRs_Address = "0001" else`
97			`PORTC when SFRs_Address = "0010" else`
98			`PORTD; --when SFRs_Address = "0011"`
99
100			`DATA <= data_read when (Q1 = '1' and RE = '1') else`
101			`(others => 'Z');`
102
103
104			`-- IO PORTs assignements ---------------------------------`
105
106			`PORA : process(TRISA, LATA)`
107			`begin`
108			`for i in 0 to 7 loop`
109			`if TRISA(i) = '0' then`
110			`PORTA(i) <= LATA(i);`
111			`else`
112			`PORTA(i) <= 'Z';`
113			`end if;`
114			`end loop;`
115			`end process;`
116
117			`PORB : process(TRISB, LATB)`
118			`begin`
119			`for i in 0 to 7 loop`
120			`if TRISB(i) = '0' then`
121			`PORTB(i) <= LATB(i);`
122			`else`
123			`PORTB(i) <= 'Z';`
124			`end if;`
125			`end loop;`
126			`end process;`
127
128			`PORC : process(TRISC, LATC)`
129			`begin`
130			`for i in 0 to 7 loop`
131			`if TRISC(i) = '0' then`
132			`PORTC(i) <= LATC(i);`
133			`else`
134			`PORTC(i) <= 'Z';`
135			`end if;`
136			`end loop;`
137			`end process;`
138
139			`PORD : process(TRISD, LATD)`
140			`begin`
141			`for i in 0 to 7 loop`
142			`if TRISD(i) = '0' then`
143			`PORTD(i) <= LATD(i);`
144			`else`
145			`PORTD(i) <= 'Z';`
146			`end if;`
147			`end loop;`
148			`end process;`
149
150
151			`end Behavioral;`

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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [PORTs.vhd] - Blame information for rev 4