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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Program_Counter.vhd] - Blame information for rev 4

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-- Company:        Ferhat Abbas University - Algeria
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-- Engineer:       Ibrahim MEZZAH
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-- Progect Supervisor: Dr H. Chemali
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-- Create Date:    19:22:33 05/19/05
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-- Design Name:    Program Counter
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-- Module Name:    Program_Counter - Counter
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-- Project Name:   Microcontroller IP (MCIP)
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-- Target Device:  xc3s500e-4fg320
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-- Tool versions:  Xilinx ISE 9.1.03i
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-- Description:  The Program Counter (PC) specifies the address
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--                 of the instruction to fetch for execution and addresses
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--                 each byte in the program memory. this module includes
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--                 also the Stack memory of 32 levels.
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-- Revision:             07/06/2008
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-- Revision  6
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-- Additional Comments: The PC structure is PCU<4:0>:PCH<7:0>:PCL<7:0>
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--                      and is equivalent to PC<20:0>.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Program_Counter is
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    Generic ( STKPTR_length : integer := 5;  -- Stack Pointer Length -- < 6
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                                  STVREN : std_logic := '1');   -- Stack Overflow/Underflow Reset Enable bit
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    Port ( nreset         : in std_logic;
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           Q2             : in std_logic;
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           Q4             : in std_logic;
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           Command_vector : in std_logic_vector(6 downto 0);
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                          Branch_data    : in std_logic_vector(11 downto 0);
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                          stack_overflow : out std_logic;
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                          IAddress       : out std_logic_vector(20 downto 1));
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end Program_Counter;
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architecture Behavioral of Program_Counter is
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component Stack_ram
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    Generic ( STKPTR_length : integer := STKPTR_length );
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         Port ( Q            : in std_logic;
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                          write_enable : in std_logic;
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                          STKPTR       : in std_logic_vector(STKPTR_length-1 downto 0);
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           Data_write   : in std_logic_vector(20 downto 1);
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           Data_read    : out std_logic_vector(20 downto 1));
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end component Stack_ram;
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        signal PCL : std_logic_vector(7 downto 1);
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        signal PCH : std_logic_vector(7 downto 0);
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        signal PCU : std_logic_vector(4 downto 0);
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        signal STKPTR : std_logic_vector(STKPTR_length-1 downto 0);
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        signal latch1      : std_logic_vector(19 downto 0);
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        signal PNTR        : std_logic_vector(STKPTR_length-1 downto 0);
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        signal PNTRp1      : std_logic_vector(STKPTR_length-1 downto 0);
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        signal pushed_addr : std_logic_vector(20 downto 1);
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        signal write_stack_enable : std_logic;
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        signal PC       : std_logic_vector(20 downto 1);
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        signal PCcall   : std_logic_vector(20 downto 1);
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        signal TOS      : std_logic_vector(20 downto 1);
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        signal PCs      : std_logic_vector(19 downto 0);
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        signal PC_addr  : std_logic_vector(19 downto 0);
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        signal offset   : std_logic_vector(19 downto 0);
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        signal Br_data  : std_logic_vector(7 downto 0);
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        alias V : std_logic_vector(6 downto 0) is Command_vector;
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        signal STKPTRfull : std_logic_vector(STKPTR_length-1 downto 0);
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        signal STKPTRzero : std_logic_vector(STKPTR_length-1 downto 0);
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begin
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stack : Stack_ram
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Port map ( Q            => Q4,
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                          write_enable => write_stack_enable,
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                          STKPTR       => PNTR,
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           Data_write   => pushed_addr,
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           Data_read    => TOS);
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        PC <= PCU&PCH&PCL;
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        PCcall <= Branch_data&Br_data;
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        PNTRp1 <= STKPTR + "1";
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        write_stack_enable <= '1'               when Command_vector(4 downto 3) = "11" else
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                                                                 '0';
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        pushed_addr <= latch1;
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        PNTR <= PNTRp1                                          when V(4 downto 3) = "11" else
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                          STKPTR;
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        STKPTRzero <= (others => '0');
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        STKPTRfull <= (others => '1');
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        offset <= "00"&x"00"&Branch_data(9 downto 0)             when V(2 downto 1) = "11" and
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                                                                                                                                                  V(5) = '0' and
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                                                                                                                                                  Branch_data(10) = '0' else
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                                 "11"&x"ff"&Branch_data(9 downto 0)              when V(2 downto 1) = "11" and
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                                                                                                                                                  V(5) = '0' and
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                                                                                                                                                  Branch_data(10) = '1' else
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                                 x"000"&Branch_data(7 downto 0)                  when V(2 downto 1) = "10" and
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                                                                                                                                                  V(5) = '0' and
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                                                                                                                                                  Branch_data(7) = '0' else
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                                 x"fff"&Branch_data(7 downto 0)                  when V(2 downto 1) = "10" and
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                                                                                                                                                  V(5) = '0' and
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                                                                                                                                                  Branch_data(7) = '1' else
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                                 x"00001";
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        PC_addr <= PCcall(20 downto 1) + "1"                    when V(5) = '1' else
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                                  PC(20 downto 1) + offset;
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        PCs <= PC_addr                                                                                  when V(0)  = '0' else
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                         latch1;
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        IAddress <= PCcall                                                                              when V(5) = '1' else
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                                   PC;
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Load_latchs : process (nreset, Q4, PCU, PCH,
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                                                          PCs, V(4), V(3), latch1, PNTRp1)
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        begin
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         if nreset = '0' then
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                 PCL     <= (others => '0');
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                 PCH     <= (others => '0');
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                 PCU     <= (others => '0');
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                 STKPTR  <= (others => '0');
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                 stack_overflow <= '0';
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         else
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         if Q4'event and Q4='1'  then
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                        PCL <= PCs(6 downto 0);
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                        PCH <= PCs(14 downto 7);
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                        PCU <= PCs(19 downto 15);
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                 if V(4) = '1' then
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                        if V(3) = '1' then                        -- PUCH --> stack
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                          if STKPTR = STKPTRfull then
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                                        if STVREN = '1' then
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                                                stack_overflow <= '1';
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                                        end if;
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                          else
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                          STKPTR <= PNTRp1;
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                          end if;
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                        else                                                              -- POP  <-- stack
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                          if STKPTR = STKPTRzero then
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                                        if STVREN = '1' then
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                                                stack_overflow <= '1';
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                                        end if;
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                          else
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                          STKPTR <= STKPTR - "1";
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                          end if;
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                        end if;
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                 end if;
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         end if;
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         end if;
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        end process;
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        process(nreset, Q2, V(6 downto 5), Branch_data,
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                          V(3), V(4), PC, TOS)
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        begin
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                 if nreset = '0' then
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                        latch1  <= (others => '0');
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                        Br_data <= (others => '0');
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                 else
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                 if Q2'event and Q2='1' then
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                        if V(6 downto 5) = "10" then
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                                Br_data <= Branch_data(7 downto 0);
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                        end if;
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                        if V(4) = '1' then
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                                if V(3) = '1' then
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                                  latch1 <= PCU&PCH&PCL;
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                                else
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                                  latch1 <= TOS; --(20 downto 1);
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                                end if;
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                         end if;
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                  end if;
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                  end if;
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        end process;
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end Behavioral;

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