OpenCores
URL https://opencores.org/ocsvn/mcip_open/mcip_open/trunk

Subversion Repositories mcip_open

[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Program_Counter.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 mezzah 
--------------------------------------------------------------------------------
2 
-- Company:        Ferhat Abbas University - Algeria
3 
-- Engineer:       Ibrahim MEZZAH
4 
-- Progect Supervisor: Dr H. Chemali
5 
-- Create Date:    19:22:33 05/19/05
6 
-- Design Name:    Program Counter
7 
-- Module Name:    Program_Counter - Counter
8 
-- Project Name:   Microcontroller IP (MCIP)
9 
-- Target Device:  xc3s500e-4fg320
10 
-- Tool versions:  Xilinx ISE 9.1.03i
11 
-- Description:  The Program Counter (PC) specifies the address
12 
--                 of the instruction to fetch for execution and addresses
13 
--                 each byte in the program memory. this module includes
14 
--                 also the Stack memory of 32 levels.
15 
-- Revision:             07/06/2008
16 
-- Revision  6
17 
-- Additional Comments: The PC structure is PCU<4:0>:PCH<7:0>:PCL<7:0>
18 
--                      and is equivalent to PC<20:0>.
19 
--------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 
 
24 
 
25 
entity Program_Counter is
26 
    Generic ( STKPTR_length : integer := 5;  -- Stack Pointer Length -- < 6
27 
                                  STVREN : std_logic := '1');   -- Stack Overflow/Underflow Reset Enable bit
28 
    Port ( nreset         : in std_logic;
29 
           Q2             : in std_logic;
30 
           Q4             : in std_logic;
31 
           Command_vector : in std_logic_vector(6 downto 0);
32 
                          Branch_data    : in std_logic_vector(11 downto 0);
33 
                          stack_overflow : out std_logic;
34 
                          IAddress       : out std_logic_vector(20 downto 1));
35 
end Program_Counter;
36 
 
37 
architecture Behavioral of Program_Counter is
38 
 
39 
component Stack_ram
40 
    Generic ( STKPTR_length : integer := STKPTR_length );
41 
         Port ( Q            : in std_logic;
42 
                          write_enable : in std_logic;
43 
                          STKPTR       : in std_logic_vector(STKPTR_length-1 downto 0);
44 
           Data_write   : in std_logic_vector(20 downto 1);
45 
           Data_read    : out std_logic_vector(20 downto 1));
46 
end component Stack_ram;
47 
 
48 
        signal PCL : std_logic_vector(7 downto 1);
49 
        signal PCH : std_logic_vector(7 downto 0);
50 
        signal PCU : std_logic_vector(4 downto 0);
51 
        signal STKPTR : std_logic_vector(STKPTR_length-1 downto 0);
52 
 
53 
        signal latch1      : std_logic_vector(19 downto 0);
54 
        signal PNTR        : std_logic_vector(STKPTR_length-1 downto 0);
55 
        signal PNTRp1      : std_logic_vector(STKPTR_length-1 downto 0);
56 
        signal pushed_addr : std_logic_vector(20 downto 1);
57 
        signal write_stack_enable : std_logic;
58 
 
59 
        signal PC       : std_logic_vector(20 downto 1);
60 
        signal PCcall   : std_logic_vector(20 downto 1);
61 
        signal TOS      : std_logic_vector(20 downto 1);
62 
        signal PCs      : std_logic_vector(19 downto 0);
63 
        signal PC_addr  : std_logic_vector(19 downto 0);
64 
        signal offset   : std_logic_vector(19 downto 0);
65 
        signal Br_data  : std_logic_vector(7 downto 0);
66 
 
67 
        alias V : std_logic_vector(6 downto 0) is Command_vector;
68 
 
69 
        signal STKPTRfull : std_logic_vector(STKPTR_length-1 downto 0);
70 
        signal STKPTRzero : std_logic_vector(STKPTR_length-1 downto 0);
71 
 
72 
begin
73 
 
74 
stack : Stack_ram
75 
Port map ( Q            => Q4,
76 
                          write_enable => write_stack_enable,
77 
                          STKPTR       => PNTR,
78 
           Data_write   => pushed_addr,
79 
           Data_read    => TOS);
80 
 
81 
        PC <= PCU&PCH&PCL;
82 
        PCcall <= Branch_data&Br_data;
83 
        PNTRp1 <= STKPTR + "1";
84 
 
85 
        write_stack_enable <= '1'               when Command_vector(4 downto 3) = "11" else
86 
                                                                 '0';
87 
        pushed_addr <= latch1;
88 
        PNTR <= PNTRp1                                          when V(4 downto 3) = "11" else
89 
                          STKPTR;
90 
 
91 
        STKPTRzero <= (others => '0');
92 
        STKPTRfull <= (others => '1');
93 
 
94 
 
95 
        offset <= "00"&x"00"&Branch_data(9 downto 0)             when V(2 downto 1) = "11" and
96 
                                                                                                                                                  V(5) = '0' and
97 
                                                                                                                                                  Branch_data(10) = '0' else
98 
                                 "11"&x"ff"&Branch_data(9 downto 0)              when V(2 downto 1) = "11" and
99 
                                                                                                                                                  V(5) = '0' and
100 
                                                                                                                                                  Branch_data(10) = '1' else
101 
                                 x"000"&Branch_data(7 downto 0)                  when V(2 downto 1) = "10" and
102 
                                                                                                                                                  V(5) = '0' and
103 
                                                                                                                                                  Branch_data(7) = '0' else
104 
                                 x"fff"&Branch_data(7 downto 0)                  when V(2 downto 1) = "10" and
105 
                                                                                                                                                  V(5) = '0' and
106 
                                                                                                                                                  Branch_data(7) = '1' else
107 
                                 x"00001";
108 
        PC_addr <= PCcall(20 downto 1) + "1"                    when V(5) = '1' else
109 
                                  PC(20 downto 1) + offset;
110 
        PCs <= PC_addr                                                                                  when V(0)  = '0' else
111 
                         latch1;
112 
 
113 
        IAddress <= PCcall                                                                              when V(5) = '1' else
114 
                                   PC;
115 
 
116 
Load_latchs : process (nreset, Q4, PCU, PCH,
117 
                                                          PCs, V(4), V(3), latch1, PNTRp1)
118 
        begin
119 
         if nreset = '0' then
120 
                 PCL     <= (others => '0');
121 
                 PCH     <= (others => '0');
122 
                 PCU     <= (others => '0');
123 
                 STKPTR  <= (others => '0');
124 
                 stack_overflow <= '0';
125 
         else
126 
         if Q4'event and Q4='1'  then
127 
                        PCL <= PCs(6 downto 0);
128 
                        PCH <= PCs(14 downto 7);
129 
                        PCU <= PCs(19 downto 15);
130 
                 if V(4) = '1' then
131 
                        if V(3) = '1' then                        -- PUCH --> stack
132 
                          if STKPTR = STKPTRfull then
133 
                                        if STVREN = '1' then
134 
                                                stack_overflow <= '1';
135 
                                        end if;
136 
                          else
137 
                          STKPTR <= PNTRp1;
138 
                          end if;
139 
                        else                                                              -- POP  <-- stack
140 
                          if STKPTR = STKPTRzero then
141 
                                        if STVREN = '1' then
142 
                                                stack_overflow <= '1';
143 
                                        end if;
144 
                          else
145 
                          STKPTR <= STKPTR - "1";
146 
                          end if;
147 
                        end if;
148 
                 end if;
149 
         end if;
150 
         end if;
151 
        end process;
152 
 
153 
        process(nreset, Q2, V(6 downto 5), Branch_data,
154 
                          V(3), V(4), PC, TOS)
155 
        begin
156 
                 if nreset = '0' then
157 
                        latch1  <= (others => '0');
158 
                        Br_data <= (others => '0');
159 
                 else
160 
                 if Q2'event and Q2='1' then
161 
                        if V(6 downto 5) = "10" then
162 
                                Br_data <= Branch_data(7 downto 0);
163 
                        end if;
164 
                        if V(4) = '1' then
165 
                                if V(3) = '1' then
166 
                                  latch1 <= PCU&PCH&PCL;
167 
                                else
168 
                                  latch1 <= TOS; --(20 downto 1);
169 
                                end if;
170 
                         end if;
171 
                  end if;
172 
                  end if;
173 
        end process;
174 
 
175 
end Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.