Subversion Repositories mcip_open

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-- Company:        Ferhat Abbas University - Algeria

-- Engineer:       Ibrahim MEZZAH

-- 

-- Create Date:    16:16:00 06/17/2013 

-- Design Name: 

-- Module Name:    Program_Memory_Controller - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Program_Memory_Controller is

         Generic (IAlength              : integer := 20; -- min = 2, max = 21

                                 pm_TOPaddr             : std_logic_vector(20 downto 0) := '0'&x"0FFFF");

    Port ( Prg_addr                     : in std_logic_vector(20 downto 0);

                          Instruction           : out std_logic_vector(15 downto 0);

                          eff_Prg_addr          : out std_logic_vector(IAlength-1 downto 0);

                          Prg_memory_bus        : in std_logic_vector(15 downto 0));

end Program_Memory_Controller;

architecture Behavioral of Program_Memory_Controller is

        signal over_address : std_logic;

begin

        over_address <= '1'                             when Prg_addr > pm_TOPaddr else

                                                 '0';

        eff_Prg_addr <= Prg_addr(IALength-1 downto 0);

        Instruction <= X"0000"                  when over_address = '1' else -- NOP

                                                Prg_memory_bus;

end Behavioral;