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mezzah |
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-- Company: Ferhat Abbas University - Algeria
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-- Engineer: Ibrahim MEZZAH
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-- Progect Supervisor: Dr H. Chemali
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-- Create Date: 01:01:08 08/01/05
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-- Design Name: Block select block
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-- Module Name: Select_bloc - selection
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-- Project Name: Microcontroller IP (MCIP)
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-- Target Device: xc3s500e-4fg320
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-- Tool versions: Xilinx ISE 9.1.03i
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-- Description: This module activate the block selected by the instruction
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-- for read or write operations.
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-- Revision: 07/07/2008
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-- Revision 1.2 - Add description
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Selection_block is
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Port ( R_W : in std_logic_vector(1 downto 0);
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Address : in std_logic_vector(11 downto 0);
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r_w_ram : out std_logic_vector(1 downto 0);
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r_w_add_pr : out std_logic_vector(1 downto 0);
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-- r_w_pc : out std_logic_vector(1 downto 0);
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r_w_opu : out std_logic_vector(1 downto 0);
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r_w_port : out std_logic_vector(1 downto 0);
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r_w_dec : out std_logic_vector(1 downto 0);
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-- r_w_tmr0 : out std_logic_vector(1 downto 0);
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-- r_w_tmr1 : out std_logic_vector(1 downto 0);
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-- r_w_tbr : out std_logic_vector(1 downto 0);
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r_w_wdt : out std_logic_vector(1 downto 0) );
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end Selection_block;
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architecture selection of Selection_block is
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begin
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process(Address, R_W)
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begin
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case Address is
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-- address provider
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-- when X"EA" => r_w_add_pr <= R_W; -- FSR0H
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"E9" => r_w_add_pr <= R_W; -- FSR0L
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"E2" => r_w_add_pr <= R_W; -- FSR1H
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"E1" => r_w_add_pr <= R_W; -- FSR1L
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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when X"FE0" => r_w_add_pr <= R_W; -- BSR
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-- r_w_pc <= "00";
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r_w_opu <= "00";
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r_w_port <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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r_w_ram <= "00";
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-- when X"DA" => r_w_add_pr <= R_W; -- FSR2H
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"D9" => r_w_add_pr <= R_W; -- FSR2L
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-- r_w_pc <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- program counter
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-- when X"FF" => r_w_pc <= R_W; -- POSU
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"FE" => r_w_pc <= R_W; -- TOSH
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"FD" => r_w_pc <= R_W; -- TOSL
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"FC" => r_w_pc <= R_W; -- STKPTR
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"FB" => r_w_pc <= R_W; -- PCLATU
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"FA" => r_w_pc <= R_W; -- PCLATH
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- when X"F9" => r_w_pc <= R_W; -- PCL
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-- r_w_add_pr <= "00";
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-- r_w_opu <= "00";
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-- r_w_port <= "00";
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-- r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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-- r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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-- r_w_ram <= "00";
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-- calcul unit
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when X"FF4" => r_w_opu <= R_W; -- PRODH
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_port <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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r_w_ram <= "00";
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when X"FF3" => r_w_opu <= R_W; -- PRODL
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_port <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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r_w_ram <= "00";
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when X"FE8" => r_w_opu <= R_W; -- WREG
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_port <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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r_w_ram <= "00";
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-- port
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when X"F95" => r_w_port <= R_W; -- TRISD
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_opu <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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-- r_w_tbr <= "00";
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| 224 |
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r_w_ram <= "00";
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when X"F94" => r_w_port <= R_W; -- TRISC
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_opu <= "00";
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r_w_dec <= "00";
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-- r_w_tmr0 <= "00";
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-- r_w_tmr1 <= "00";
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r_w_wdt <= "00";
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| 233 |
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-- r_w_tbr <= "00";
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r_w_ram <= "00";
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when X"F93" => r_w_port <= R_W; -- TRISB
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r_w_add_pr <= "00";
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-- r_w_pc <= "00";
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r_w_opu <= "00";
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| 239 |
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r_w_dec <= "00";
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| 240 |
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-- r_w_tmr0 <= "00";
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| 241 |
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-- r_w_tmr1 <= "00";
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| 242 |
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r_w_wdt <= "00";
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| 243 |
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-- r_w_tbr <= "00";
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| 244 |
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r_w_ram <= "00";
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| 245 |
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when X"F92" => r_w_port <= R_W; -- TRISA
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| 246 |
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r_w_add_pr <= "00";
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| 247 |
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-- r_w_pc <= "00";
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| 248 |
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r_w_opu <= "00";
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| 249 |
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r_w_dec <= "00";
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| 250 |
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-- r_w_tmr0 <= "00";
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| 251 |
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-- r_w_tmr1 <= "00";
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| 252 |
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r_w_wdt <= "00";
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| 253 |
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-- r_w_tbr <= "00";
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| 254 |
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r_w_ram <= "00";
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| 255 |
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when X"F8C" => r_w_port <= R_W; -- LATD
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| 256 |
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r_w_add_pr <= "00";
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| 257 |
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-- r_w_pc <= "00";
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| 258 |
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r_w_opu <= "00";
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| 259 |
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r_w_dec <= "00";
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| 260 |
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-- r_w_tmr0 <= "00";
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| 261 |
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-- r_w_tmr1 <= "00";
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| 262 |
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r_w_wdt <= "00";
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| 263 |
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-- r_w_tbr <= "00";
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| 264 |
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r_w_ram <= "00";
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| 265 |
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when X"F8B" => r_w_port <= R_W; -- LATC
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| 266 |
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r_w_add_pr <= "00";
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| 267 |
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-- r_w_pc <= "00";
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| 268 |
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r_w_opu <= "00";
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| 269 |
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r_w_dec <= "00";
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| 270 |
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-- r_w_tmr0 <= "00";
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| 271 |
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-- r_w_tmr1 <= "00";
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| 272 |
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r_w_wdt <= "00";
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| 273 |
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-- r_w_tbr <= "00";
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| 274 |
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r_w_ram <= "00";
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| 275 |
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when X"F8A" => r_w_port <= R_W; -- LATB
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| 276 |
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r_w_add_pr <= "00";
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| 277 |
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-- r_w_pc <= "00";
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| 278 |
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r_w_opu <= "00";
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| 279 |
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r_w_dec <= "00";
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| 280 |
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-- r_w_tmr0 <= "00";
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| 281 |
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-- r_w_tmr1 <= "00";
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| 282 |
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r_w_wdt <= "00";
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| 283 |
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-- r_w_tbr <= "00";
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| 284 |
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r_w_ram <= "00";
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| 285 |
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when X"F89" => r_w_port <= R_W; -- LATA
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| 286 |
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r_w_add_pr <= "00";
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| 287 |
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-- r_w_pc <= "00";
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| 288 |
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r_w_opu <= "00";
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| 289 |
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r_w_dec <= "00";
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| 290 |
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-- r_w_tmr0 <= "00";
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| 291 |
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-- r_w_tmr1 <= "00";
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| 292 |
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r_w_wdt <= "00";
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| 293 |
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-- r_w_tbr <= "00";
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| 294 |
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r_w_ram <= "00";
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| 295 |
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when X"F83" => r_w_port <= R_W; -- PORTD
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| 296 |
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r_w_add_pr <= "00";
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| 297 |
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-- r_w_pc <= "00";
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| 298 |
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r_w_opu <= "00";
|
| 299 |
|
|
r_w_dec <= "00";
|
| 300 |
|
|
-- r_w_tmr0 <= "00";
|
| 301 |
|
|
-- r_w_tmr1 <= "00";
|
| 302 |
|
|
r_w_wdt <= "00";
|
| 303 |
|
|
-- r_w_tbr <= "00";
|
| 304 |
|
|
r_w_ram <= "00";
|
| 305 |
|
|
when X"F82" => r_w_port <= R_W; -- PORTC
|
| 306 |
|
|
r_w_add_pr <= "00";
|
| 307 |
|
|
-- r_w_pc <= "00";
|
| 308 |
|
|
r_w_opu <= "00";
|
| 309 |
|
|
r_w_dec <= "00";
|
| 310 |
|
|
-- r_w_tmr0 <= "00";
|
| 311 |
|
|
-- r_w_tmr1 <= "00";
|
| 312 |
|
|
r_w_wdt <= "00";
|
| 313 |
|
|
-- r_w_tbr <= "00";
|
| 314 |
|
|
r_w_ram <= "00";
|
| 315 |
|
|
when X"F81" => r_w_port <= R_W; -- PORTB
|
| 316 |
|
|
r_w_add_pr <= "00";
|
| 317 |
|
|
-- r_w_pc <= "00";
|
| 318 |
|
|
r_w_opu <= "00";
|
| 319 |
|
|
r_w_dec <= "00";
|
| 320 |
|
|
-- r_w_tmr0 <= "00";
|
| 321 |
|
|
-- r_w_tmr1 <= "00";
|
| 322 |
|
|
r_w_wdt <= "00";
|
| 323 |
|
|
-- r_w_tbr <= "00";
|
| 324 |
|
|
r_w_ram <= "00";
|
| 325 |
|
|
when X"F80" => r_w_port <= R_W; -- PORTA
|
| 326 |
|
|
r_w_add_pr <= "00";
|
| 327 |
|
|
-- r_w_pc <= "00";
|
| 328 |
|
|
r_w_opu <= "00";
|
| 329 |
|
|
r_w_dec <= "00";
|
| 330 |
|
|
-- r_w_tmr0 <= "00";
|
| 331 |
|
|
-- r_w_tmr1 <= "00";
|
| 332 |
|
|
r_w_wdt <= "00";
|
| 333 |
|
|
-- r_w_tbr <= "00";
|
| 334 |
|
|
r_w_ram <= "00";
|
| 335 |
|
|
-- decoder
|
| 336 |
|
|
-- when X"F2" => r_w_dec <= R_W; -- INTCON
|
| 337 |
|
|
-- r_w_add_pr <= "00";
|
| 338 |
|
|
-- r_w_pc <= "00";
|
| 339 |
|
|
-- r_w_opu <= "00";
|
| 340 |
|
|
-- r_w_port <= "00";
|
| 341 |
|
|
-- r_w_tmr0 <= "00";
|
| 342 |
|
|
-- r_w_tmr1 <= "00";
|
| 343 |
|
|
-- r_w_wdt <= "00";
|
| 344 |
|
|
-- r_w_tbr <= "00";
|
| 345 |
|
|
-- r_w_ram <= "00";
|
| 346 |
|
|
-- when X"F1" => r_w_dec <= R_W; -- INTCON2
|
| 347 |
|
|
-- r_w_add_pr <= "00";
|
| 348 |
|
|
-- r_w_pc <= "00";
|
| 349 |
|
|
-- r_w_opu <= "00";
|
| 350 |
|
|
-- r_w_port <= "00";
|
| 351 |
|
|
-- r_w_tmr0 <= "00";
|
| 352 |
|
|
-- r_w_tmr1 <= "00";
|
| 353 |
|
|
-- r_w_wdt <= "00";
|
| 354 |
|
|
-- r_w_tbr <= "00";
|
| 355 |
|
|
-- r_w_ram <= "00";
|
| 356 |
|
|
-- when X"F0" => r_w_dec <= R_W; -- INTCON3
|
| 357 |
|
|
-- r_w_add_pr <= "00";
|
| 358 |
|
|
-- r_w_pc <= "00";
|
| 359 |
|
|
-- r_w_opu <= "00";
|
| 360 |
|
|
-- r_w_port <= "00";
|
| 361 |
|
|
-- r_w_tmr0 <= "00";
|
| 362 |
|
|
-- r_w_tmr1 <= "00";
|
| 363 |
|
|
-- r_w_wdt <= "00";
|
| 364 |
|
|
-- r_w_tbr <= "00";
|
| 365 |
|
|
-- r_w_ram <= "00";
|
| 366 |
|
|
when X"FD8" => r_w_dec <= R_W; -- STATUS
|
| 367 |
|
|
r_w_add_pr <= "00";
|
| 368 |
|
|
-- r_w_pc <= "00";
|
| 369 |
|
|
r_w_opu <= "00";
|
| 370 |
|
|
r_w_port <= "00";
|
| 371 |
|
|
-- r_w_tmr0 <= "00";
|
| 372 |
|
|
-- r_w_tmr1 <= "00";
|
| 373 |
|
|
r_w_wdt <= "00";
|
| 374 |
|
|
-- r_w_tbr <= "00";
|
| 375 |
|
|
r_w_ram <= "00";
|
| 376 |
|
|
-- timer0
|
| 377 |
|
|
-- when X"D7" => r_w_tmr0 <= R_W; -- TMR0H
|
| 378 |
|
|
-- r_w_add_pr <= "00";
|
| 379 |
|
|
-- r_w_pc <= "00";
|
| 380 |
|
|
-- r_w_opu <= "00";
|
| 381 |
|
|
-- r_w_port <= "00";
|
| 382 |
|
|
-- r_w_dec <= "00";
|
| 383 |
|
|
-- r_w_tmr1 <= "00";
|
| 384 |
|
|
-- r_w_wdt <= "00";
|
| 385 |
|
|
-- r_w_tbr <= "00";
|
| 386 |
|
|
-- r_w_ram <= "00";
|
| 387 |
|
|
-- when X"D6" => r_w_tmr0 <= R_W; -- TMR0L
|
| 388 |
|
|
-- r_w_add_pr <= "00";
|
| 389 |
|
|
-- r_w_pc <= "00";
|
| 390 |
|
|
-- r_w_opu <= "00";
|
| 391 |
|
|
-- r_w_port <= "00";
|
| 392 |
|
|
-- r_w_dec <= "00";
|
| 393 |
|
|
-- r_w_tmr1 <= "00";
|
| 394 |
|
|
-- r_w_wdt <= "00";
|
| 395 |
|
|
-- r_w_tbr <= "00";
|
| 396 |
|
|
-- r_w_ram <= "00";
|
| 397 |
|
|
-- when X"D5" => r_w_tmr0 <= R_W; -- T0CON
|
| 398 |
|
|
-- r_w_add_pr <= "00";
|
| 399 |
|
|
-- r_w_pc <= "00";
|
| 400 |
|
|
-- r_w_opu <= "00";
|
| 401 |
|
|
-- r_w_port <= "00";
|
| 402 |
|
|
-- r_w_dec <= "00";
|
| 403 |
|
|
-- r_w_tmr1 <= "00";
|
| 404 |
|
|
-- r_w_wdt <= "00";
|
| 405 |
|
|
-- r_w_tbr <= "00";
|
| 406 |
|
|
-- r_w_ram <= "00";
|
| 407 |
|
|
-- -- timer1
|
| 408 |
|
|
-- when X"CF" => r_w_tmr1 <= R_W; -- TMR1H
|
| 409 |
|
|
-- r_w_add_pr <= "00";
|
| 410 |
|
|
-- r_w_pc <= "00";
|
| 411 |
|
|
-- r_w_opu <= "00";
|
| 412 |
|
|
-- r_w_port <= "00";
|
| 413 |
|
|
-- r_w_dec <= "00";
|
| 414 |
|
|
-- r_w_tmr0 <= "00";
|
| 415 |
|
|
-- r_w_wdt <= "00";
|
| 416 |
|
|
-- r_w_tbr <= "00";
|
| 417 |
|
|
-- r_w_ram <= "00";
|
| 418 |
|
|
-- when X"CE" => r_w_tmr1 <= R_W; -- TMR1L
|
| 419 |
|
|
-- r_w_add_pr <= "00";
|
| 420 |
|
|
-- r_w_pc <= "00";
|
| 421 |
|
|
-- r_w_opu <= "00";
|
| 422 |
|
|
-- r_w_port <= "00";
|
| 423 |
|
|
-- r_w_dec <= "00";
|
| 424 |
|
|
-- r_w_tmr0 <= "00";
|
| 425 |
|
|
-- r_w_wdt <= "00";
|
| 426 |
|
|
-- r_w_tbr <= "00";
|
| 427 |
|
|
-- r_w_ram <= "00";
|
| 428 |
|
|
-- when X"CD" => r_w_tmr1 <= R_W; -- T1CON
|
| 429 |
|
|
-- r_w_add_pr <= "00";
|
| 430 |
|
|
-- r_w_pc <= "00";
|
| 431 |
|
|
-- r_w_opu <= "00";
|
| 432 |
|
|
-- r_w_port <= "00";
|
| 433 |
|
|
-- r_w_dec <= "00";
|
| 434 |
|
|
-- r_w_tmr0 <= "00";
|
| 435 |
|
|
-- r_w_wdt <= "00";
|
| 436 |
|
|
-- r_w_tbr <= "00";
|
| 437 |
|
|
-- r_w_ram <= "00";
|
| 438 |
|
|
-- watchdog
|
| 439 |
|
|
when X"FC0" => r_w_wdt <= R_W; -- WDTCON
|
| 440 |
|
|
r_w_add_pr <= "00";
|
| 441 |
|
|
-- r_w_pc <= "00";
|
| 442 |
|
|
r_w_opu <= "00";
|
| 443 |
|
|
r_w_port <= "00";
|
| 444 |
|
|
r_w_dec <= "00";
|
| 445 |
|
|
-- r_w_tmr0 <= "00";
|
| 446 |
|
|
-- r_w_tmr1 <= "00";
|
| 447 |
|
|
-- r_w_tbr <= "00";
|
| 448 |
|
|
r_w_ram <= "00";
|
| 449 |
|
|
-- table read
|
| 450 |
|
|
-- when X"F8" => r_w_tbr <= R_W; -- TBLPTRU
|
| 451 |
|
|
-- r_w_add_pr <= "00";
|
| 452 |
|
|
-- r_w_pc <= "00";
|
| 453 |
|
|
-- r_w_opu <= "00";
|
| 454 |
|
|
-- r_w_port <= "00";
|
| 455 |
|
|
-- r_w_dec <= "00";
|
| 456 |
|
|
-- r_w_tmr0 <= "00";
|
| 457 |
|
|
-- r_w_tmr1 <= "00";
|
| 458 |
|
|
-- r_w_wdt <= "00";
|
| 459 |
|
|
-- r_w_ram <= "00";
|
| 460 |
|
|
-- when X"F7" => r_w_tbr <= R_W; -- TBLPTRH
|
| 461 |
|
|
-- r_w_add_pr <= "00";
|
| 462 |
|
|
-- r_w_pc <= "00";
|
| 463 |
|
|
-- r_w_opu <= "00";
|
| 464 |
|
|
-- r_w_port <= "00";
|
| 465 |
|
|
-- r_w_dec <= "00";
|
| 466 |
|
|
-- r_w_tmr0 <= "00";
|
| 467 |
|
|
-- r_w_tmr1 <= "00";
|
| 468 |
|
|
-- r_w_wdt <= "00";
|
| 469 |
|
|
-- r_w_ram <= "00";
|
| 470 |
|
|
-- when X"F6" => r_w_tbr <= R_W; -- TBLPTRL
|
| 471 |
|
|
-- r_w_add_pr <= "00";
|
| 472 |
|
|
-- r_w_pc <= "00";
|
| 473 |
|
|
-- r_w_opu <= "00";
|
| 474 |
|
|
-- r_w_port <= "00";
|
| 475 |
|
|
-- r_w_dec <= "00";
|
| 476 |
|
|
-- r_w_tmr0 <= "00";
|
| 477 |
|
|
-- r_w_tmr1 <= "00";
|
| 478 |
|
|
-- r_w_wdt <= "00";
|
| 479 |
|
|
-- r_w_ram <= "00";
|
| 480 |
|
|
-- when X"F5" => r_w_tbr <= R_W; -- TABLAT
|
| 481 |
|
|
-- r_w_add_pr <= "00";
|
| 482 |
|
|
-- r_w_pc <= "00";
|
| 483 |
|
|
-- r_w_opu <= "00";
|
| 484 |
|
|
-- r_w_port <= "00";
|
| 485 |
|
|
-- r_w_dec <= "00";
|
| 486 |
|
|
-- r_w_tmr0 <= "00";
|
| 487 |
|
|
-- r_w_tmr1 <= "00";
|
| 488 |
|
|
-- r_w_wdt <= "00";
|
| 489 |
|
|
-- r_w_ram <= "00";
|
| 490 |
|
|
-- ram
|
| 491 |
|
|
when others=> r_w_ram <= R_W; -- RAM
|
| 492 |
|
|
r_w_add_pr <= "00";
|
| 493 |
|
|
-- r_w_pc <= "00";
|
| 494 |
|
|
r_w_opu <= "00";
|
| 495 |
|
|
r_w_port <= "00";
|
| 496 |
|
|
r_w_dec <= "00";
|
| 497 |
|
|
-- r_w_tmr0 <= "00";
|
| 498 |
|
|
-- r_w_tmr1 <= "00";
|
| 499 |
|
|
r_w_wdt <= "00";
|
| 500 |
|
|
-- r_w_tbr <= "00";
|
| 501 |
|
|
end case;
|
| 502 |
|
|
end process;
|
| 503 |
|
|
|
| 504 |
|
|
end selection;
|
