URL https://opencores.org/ocsvn/mcip_open/mcip_open/trunk

Subversion Repositories mcip_open

[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [iseconfig/] [MCIPopen.projectmgr] - Blame information for rev 4

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         2
         /IP_Basic_Core - mapping D:|Doctorat|Projets VHDL|MCIPopen|IP_Core.vhd/CPU_block - CPU - CPUnit
         /IP_Basic_Core - mapping D:|Doctorat|Projets VHDL|MCIPopen|IP_Core.vhd/RPW_block - RPW - Behavioral
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen.vhd/CPU_block - CPU - CPUnit
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen.vhd/CPU_block - CPU - CPUnit/InstructionDecoder - Instruction_Decoder - Decode_Control
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen.vhd/CPU_block - CPU - CPUnit/OperationUnit - Operation_Unit - Behavioral
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen.vhd/CPU_block - CPU - CPUnit/OperationUnit - Operation_Unit - Calcul/ALUnit - ALU - simple
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen.vhd/CPU_block - CPU - CPUnit/PC - Program_Counter - Behavioral
         /MCIPopen_mcu_example - Behavioral D:|Doctorat|Projets VHDL|MCIPopen|MCIPopen_mcu_example.vhd/MCIPcore - MCIPopen - mapping
      
      
         MCIPopen_mcu_example - Behavioral (D:/Doctorat/Projets VHDL/MCIPopen/MCIPopen_mcu_example.vhd)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000029d0000000100000003000000000000000100000003
      true
      MCIPopen_mcu_example - Behavioral (D:/Doctorat/Projets VHDL/MCIPopen/MCIPopen_mcu_example.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff0000000000000001000000000000000001000000000000000000000000000000000000027d000000040101000100000000000000000000000064ffffffff000000810000000000000004000000aa0000000100000000000000240000000100000000000000660000000100000000000001490000000100000000
      false
      Address_Provider.vhd
   
   
      
         1
      
      
         Use_Pack.vhd
      
      8
      0
      000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      Use_Pack.vhd
   
   000000ff0000000000000002000000f2000000ae01000000050100000002
   Implementation
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design
         User Constraints
      
      
         Synthesize - XST
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000
      false
      Synthesize - XST
   
   
      
         2
         /MCIPopen - mapping D:|Doctorat|Projets VHDL|MCIPopen|IP_Core.vhd
         /tb_PORTs - behavior D:|Doctorat|Projets VHDL|MCIPopen|tb_PORTs.vhd
         /tb_testOldMCIP - behavior D:|Doctorat|Projets VHDL|MCIPopen|tb_testOldMCIP.vhd/uut - IP_Basic_Core - mapping
         /tb_testOldMCIP - behavior D:|Doctorat|Projets VHDL|MCIPopen|tb_testOldMCIP.vhd/uut - MCIPopen - mapping/CPU_block - CPU - CPUnit
      
      
         tb_PLL - behavior (D:/Doctorat/Projets VHDL/MCIPopen/tb_PLL.vhd)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000017b000000020000000000000000000000000200000064ffffffff0000008100000003000000020000017b0000000100000003000000000000000100000003
      true
      tb_PLL - behavior (D:/Doctorat/Projets VHDL/MCIPopen/tb_PLL.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      
   
   
      
         1
      
      
         Behavioral Check Syntax
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      Behavioral Check Syntax
   


Line No.	Rev	Author	Line
1	4	mezzah
2
3
4
5
6
7
8
9			`2`
10			`/IP_Basic_Core - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|IP_Core.vhd/CPU_block - CPU - CPUnit`
11			`/IP_Basic_Core - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|IP_Core.vhd/RPW_block - RPW - Behavioral`
12			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen.vhd/CPU_block - CPU - CPUnit`
13			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen.vhd/CPU_block - CPU - CPUnit/InstructionDecoder - Instruction_Decoder - Decode_Control`
14			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen.vhd/CPU_block - CPU - CPUnit/OperationUnit - Operation_Unit - Behavioral`
15			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen.vhd/CPU_block - CPU - CPUnit/OperationUnit - Operation_Unit - Calcul/ALUnit - ALU - simple`
16			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen.vhd/CPU_block - CPU - CPUnit/PC - Program_Counter - Behavioral`
17			`/MCIPopen_mcu_example - Behavioral D:\|Doctorat\|Projets VHDL\|MCIPopen\|MCIPopen_mcu_example.vhd/MCIPcore - MCIPopen - mapping`
18
19
20			`MCIPopen_mcu_example - Behavioral (D:/Doctorat/Projets VHDL/MCIPopen/MCIPopen_mcu_example.vhd)`
21
22			`0`
23			`0`
24			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000029d0000000100000003000000000000000100000003`
25			`true`
26			`MCIPopen_mcu_example - Behavioral (D:/Doctorat/Projets VHDL/MCIPopen/MCIPopen_mcu_example.vhd)`
27
28
29
30			`1`
31			`Design Utilities`
32
33
34
35
36			`0`
37			`0`
38			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
39			`false`
40
41
42
43
44			`1`
45
46
47			`0`
48			`0`
49			`000000ff0000000000000001000000000000000001000000000000000000000000000000000000027d000000040101000100000000000000000000000064ffffffff000000810000000000000004000000aa0000000100000000000000240000000100000000000000660000000100000000000001490000000100000000`
50			`false`
51			`Address_Provider.vhd`
52
53
54
55			`1`
56
57
58			`Use_Pack.vhd`
59
60			`8`
61			`0`
62			`000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
63			`false`
64			`Use_Pack.vhd`
65
66			`000000ff0000000000000002000000f2000000ae01000000050100000002`
67			`Implementation`
68
69
70			`1`
71			`Configure Target Device`
72			`Design Utilities`
73			`Implement Design`
74			`User Constraints`
75
76
77			`Synthesize - XST`
78
79			`0`
80			`0`
81			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000`
82			`false`
83			`Synthesize - XST`
84
85
86
87			`2`
88			`/MCIPopen - mapping D:\|Doctorat\|Projets VHDL\|MCIPopen\|IP_Core.vhd`
89			`/tb_PORTs - behavior D:\|Doctorat\|Projets VHDL\|MCIPopen\|tb_PORTs.vhd`
90			`/tb_testOldMCIP - behavior D:\|Doctorat\|Projets VHDL\|MCIPopen\|tb_testOldMCIP.vhd/uut - IP_Basic_Core - mapping`
91			`/tb_testOldMCIP - behavior D:\|Doctorat\|Projets VHDL\|MCIPopen\|tb_testOldMCIP.vhd/uut - MCIPopen - mapping/CPU_block - CPU - CPUnit`
92
93
94			`tb_PLL - behavior (D:/Doctorat/Projets VHDL/MCIPopen/tb_PLL.vhd)`
95
96			`0`
97			`0`
98			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000017b000000020000000000000000000000000200000064ffffffff0000008100000003000000020000017b0000000100000003000000000000000100000003`
99			`true`
100			`tb_PLL - behavior (D:/Doctorat/Projets VHDL/MCIPopen/tb_PLL.vhd)`
101
102
103
104			`1`
105			`Design Utilities`
106
107
108
109
110			`0`
111			`0`
112			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
113			`false`
114
115
116
117
118			`1`
119
120
121			`Behavioral Check Syntax`
122
123			`0`
124			`0`
125			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
126			`false`
127			`Behavioral Check Syntax`
128
129

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Subversion Repositories mcip_open

[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [iseconfig/] [MCIPopen.projectmgr] - Blame information for rev 4