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-- Company:        Ferhat Abbas University - Algeria

-- Engineer:       Ibrahim MEZZAH

-- 

-- Create Date:    17:56:57 04/12/2012 

-- Design Name: 

-- Module Name:    Watchdog - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Watchdog is

         Generic(WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits

                                WDTEN : std_logic := '0'); -- Watchdog Timer enable bit

    Port ( nreset       : in std_logic;

           WDT_clock    : in std_logic;

           Q1           : in std_logic;

           Q4           : in std_logic;

           RE           : in std_logic;

           WE           : in std_logic;

           clrWDT       : in std_logic;

           Sleep                   : in std_logic;

           DATA         : inout std_logic_vector(7 downto 0);

           WDT_reset    : out std_logic;

           WDTwake_up   : out std_logic);

end Watchdog;

architecture Behavioral of Watchdog is

  signal data_write_0 : std_logic;

  signal data_read : std_logic_vector(7 downto 0);

  signal SWDTEN : std_logic;

  signal Reset : std_logic;

  signal Wake_up : std_logic;

  signal Sleep_state : std_logic;

  signal WDT_Posts_counter : std_logic_vector(conv_integer(WDTPS)+6 downto 0);

  signal Postscaler_output : std_logic;

begin

        data_read <= "0000000"&SWDTEN; -- WDTCON

        data_write_0 <= DATA(0);

        DATA <= data_read                                                        when RE = '1' and Q1 = '1' else

                          (others => 'Z');

        Postscaler_output <= WDT_Posts_counter(conv_integer(WDTPS)+6);

        WDTCON : process(nreset, Q4, WE, data_write_0)

        begin

                if nreset = '0' then

                                SWDTEN <= WDTEN;

                elsif Q4'event and Q4 = '1' then

                        if WE = '1' then

                                SWDTEN <= data_write_0;

                        else

                                SWDTEN <= SWDTEN;

                        end if;

                end if;

        end process;

        Counter : process(nreset, SWDTEN, Sleep, WDT_clock, clrWDT, Sleep_state)

        begin

          if nreset = '0' or SWDTEN = '0' or (Sleep = '1' and Sleep_state = '0') or clrWDT = '1' then

                        WDT_Posts_counter <= (others => '0');

          elsif WDT_clock'event and WDT_clock = '0' then

                        WDT_Posts_counter <= WDT_Posts_counter + "1";

          end if;

        end process;

        Sleep_control : process(nreset, Sleep, Q4)

        begin

          if nreset = '0' or Sleep = '0' then

                        Sleep_state <= '0';

          elsif Q4'event and Q4 = '0' then

                        Sleep_state <= '1';

          end if;

        end process;

        WakeUp : process(nreset, Postscaler_output, Sleep)

        begin

          if nreset = '0' or Sleep = '0' then

                        Wake_up <= '0';

          elsif Postscaler_output'event and Postscaler_output = '0' then

                        Wake_up <= '1';

          end if;

        end process;

        Reset_signal : process(nreset, Postscaler_output, Sleep)

        begin

          if nreset = '0' or Sleep = '1' then

                        Reset <= '0';

          elsif Postscaler_output'event and Postscaler_output = '0' then

                        Reset <= '1';

          end if;

        end process;

        WDT_reset <= Reset;

        WDTwake_up <= Wake_up;

end Behavioral;