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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [common/] [counter.v] - Blame information for rev 5

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`timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////
// 
// 4004 Counter sub-module
// 
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
// 
// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// 
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
// 
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
 
module counter(
        input  wire     sysclk,
        input  wire     step_a,
        input  wire     step_b,
        output reg      q = 1'b0
        );
 
        reg q_n = 1'b1;
        always @(posedge sysclk) begin
                if (step_a)     q <= ~q_n;
                if (step_b) q_n <= q;
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	rrpollack	`timescale 1ns / 1ps
2			`default_nettype none
3			`////////////////////////////////////////////////////////////////////////`
4			`//`
5			`// 4004 Counter sub-module`
6			`//`
7			`// This file is part of the MCS-4 project hosted at OpenCores:`
8			`// http://www.opencores.org/cores/mcs-4/`
9			`//`
10	4	rrpollack	`// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>`
11	2	rrpollack	`//`
12			`// These materials are provided under the Creative Commons`
13			`// "Attribution-NonCommercial-ShareAlike" Public License. They`
14			`// are NOT "public domain" and are protected by copyright.`
15			`//`
16			`// This work based on materials provided by Intel Corporation and`
17			`// others under the same license. See the file doc/License for`
18			`// details of this license.`
19			`//`
20			`////////////////////////////////////////////////////////////////////////`
21
22			`module counter(`
23			`input wire sysclk,`
24			`input wire step_a,`
25			`input wire step_b,`
26			`output reg q = 1'b0`
27			`);`
28
29			`reg q_n = 1'b1;`
30			`always @(posedge sysclk) begin`
31			`if (step_a) q <= ~q_n;`
32			`if (step_b) q_n <= q;`
33			`end`
34
35			`endmodule`

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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [common/] [counter.v] - Blame information for rev 5