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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4001/] [i4001_rom.v] - Blame information for rev 6

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1 6 rrpollack
`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// MCS-4 i4001 shared ROM storage
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//
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// This module emulates the Intel 4001 ROM storage. It is separate from
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// the "i4001" module to make efficient use of FPGA block ram resources.
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// One i4001_rom instantiation can be connected to multiple "i4001"
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// modules via a rom_addr / rom_data bus.
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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//      http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// They are NOT "public domain", and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module i4001_rom #(
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    parameter       ROM_FILE    = "i4001-0.mem",
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    parameter [3:0] ROM_NUMBER  = 4'd0,
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    parameter       ROM_SIZE    = 2048
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    ) (
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    input  wire         sysclk,
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    input  wire [11:0]  rom_addr,
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    output reg  [ 7:0]  rom_data
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    );
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    (* rom_style="block" *)
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    reg [7:0]   rom_array [0:ROM_SIZE-1];
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    initial begin
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        $readmemh (ROM_FILE, rom_array);
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    end
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    wire [11:0] array_addr = {rom_addr[11:8] - ROM_NUMBER,
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                              rom_addr[ 7:0]};
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    // Block RAMs have synchronous read ports
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    // that require a clock to read the array
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    always @(posedge sysclk) begin
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        rom_data <= rom_array[array_addr];
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    end
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endmodule

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