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rrpollack |
`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// MCS-4 i4002 RAM storage
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//
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// This module defines the RAM allocated to a single i4002 register,
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// containing 16x4-bit "main" memory array and a 4x4-bit "status"
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// array. An i4002 RAM chip contains four of these RAM register modules.
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//
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// This implementation allocates a single 20x4-bit dual-port
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// RAM: ram_array. The "main" memory array is represented by the
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// elements [0:15] of ram_array, while the "status" array is
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// represented by elements [16:19].
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//
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// This module defines a dual-port array to allow the VFD driver access
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// to the "Working Register", WR, which is stored in RAM0 register 1.
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// The synthesis tools should recognize theinstantiations that do not
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// need to be dual-port and trim the unneeded logic and storage.
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// They are NOT "public domain", and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module i4002_ram #(
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parameter RAM_ARRAY_SIZE = 32 // Size of the RAM array
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) (
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input wire sysclk,
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input wire [4:0] addr, // Address
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input wire write, // Write Enable
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input wire [3:0] data_in, // Data input to write
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output wire [3:0] data_out, // Data output (unregistered)
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input wire [4:0] addr2, // 2nd port address
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output wire [3:0] data2_out // 2nd port data output (unregisted)
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);
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//
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// Infer a 32x4 distributed dual-port RAM
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//
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// The "status" characters are stored in [16:19]
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//
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(* ram_style="distributed" *)
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reg [3:0] ram_array [0:(RAM_ARRAY_SIZE-1)];
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always @(posedge sysclk) begin
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if (write) begin
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ram_array[addr] <= data_in;
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end
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end
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assign data_out = ram_array[addr];
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assign data2_out = ram_array[addr2];
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`ifdef XILINX_ISIM
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// Pre-initialize the RAM
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genvar i;
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generate
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for (i = 0; i < RAM_ARRAY_SIZE; i = i + 1) begin : initial_ram
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initial ram_array[i] = 4'bxxxx;
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end
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endgenerate
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`endif
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endmodule
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