1 |
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dimo |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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4 |
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use work.asci_types.all;
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5 |
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ENTITY lcd1 IS
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generic( one_usec_factor : INTEGER := 1e2/2-1; -- 1e8/2-1 for 1s period @ 100 MHz
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max_factor : INTEGER := 100000; -- the longest delay needed (init. time)
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init_factor : INTEGER := 100000; -- 100 ms, initialization time
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normal_factor : INTEGER := 50; -- 50 us, standard waiting time
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extended_factor : INTEGER := 2000; -- 2 ms, waiting time after clear display and cursor at home commands
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constant ext_mode : std_logic_vector(9 downto 0) := "0000110100"; -- goto extension mode
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constant lines_4 : std_logic_vector(9 downto 0) := "0000001001"; -- 4 lines, 5x8 font, goto normal mode
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constant data_8bit : std_logic_vector(9 downto 0) := "0000110000"; -- 8 bit data
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constant display_on : std_logic_vector(9 downto 0) := "0000001100"; -- display on, cursos off, blinking off
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constant display_clear : std_logic_vector(9 downto 0) := "0000000001"; -- clear display
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constant entry_mode : std_logic_vector(9 downto 0) := "0000000110" -- goto entry mode
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);
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port( clk_400, clk, rst : IN std_logic; -- low active reset, clk_400 has a 4 us period
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lcd_rs : OUT std_logic; -- H=data L=command
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lcd_rw : OUT std_logic; -- H=read L=write
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lcd_ena : OUT STD_LOGIC;
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lcd_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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led : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); -- used for debug purposes
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END lcd1;
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ARCHITECTURE behavioral OF lcd1 IS
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TYPE state IS ( init_start, wait_set1, set1, wait_eset, eset, wait_set2, set2, wait_lcd_on,
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lcd_on, wait_lcd_clear, lcd_clear, wait_lcd_entr, lcd_entr,
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wait_l1s1, l1s1, wait_l1s2, l1s2, wait_l1s3, l1s3, wait_l1s4, l1s4, wait_l1s5, l1s5,
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wait_l1s6, l1s6, wait_l1s7, l1s7, wait_l1s8, l1s8, wait_l1s9, l1s9, wait_l1s10, l1s10,
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wait_l1s11, l1s11, wait_l1s12, l1s12, wait_l1s13, l1s13, wait_l1s14, l1s14, wait_l1s15, l1s15,
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wait_l1s16, l1s16, wait_l1s17, l1s17, wait_l1s18, l1s18, wait_l1s19, l1s19, wait_l1s20, l1s20,
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wait_l2s1, l2s1, wait_l2s2, l2s2, wait_l2s3, l2s3, wait_l2s4, l2s4, wait_l2s5, l2s5,
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wait_l2s6, l2s6, wait_l2s7, l2s7, wait_l2s8, l2s8, wait_l2s9, l2s9, wait_l2s10, l2s10,
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wait_l2s11, l2s11, wait_l2s12, l2s12, wait_l2s13, l2s13, wait_l2s14, l2s14, wait_l2s15, l2s15,
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wait_l2s16, l2s16, wait_l2s17, l2s17, wait_l2s18, l2s18, wait_l2s19, l2s19, wait_l2s20, l2s20,
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wait_l3s1, l3s1, wait_l3s2, l3s2, wait_l3s3, l3s3, wait_l3s4, l3s4, wait_l3s5, l3s5,
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wait_l3s6, l3s6, wait_l3s7, l3s7, wait_l3s8, l3s8, wait_l3s9, l3s9, wait_l3s10, l3s10,
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wait_l3s11, l3s11, wait_l3s12, l3s12, wait_l3s13, l3s13, wait_l3s14, l3s14, wait_l3s15, l3s15,
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wait_l3s16, l3s16, wait_l3s17, l3s17, wait_l3s18, l3s18, wait_l3s19, l3s19, wait_l3s20, l3s20,
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wait_l4s1, l4s1, wait_l4s2, l4s2, wait_l4s3, l4s3, wait_l4s4, l4s4, wait_l4s5, l4s5,
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wait_l4s6, l4s6, wait_l4s7, l4s7, wait_l4s8, l4s8, wait_l4s9, l4s9, wait_l4s10, l4s10,
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wait_l4s11, l4s11, wait_l4s12, l4s12, wait_l4s13, l4s13, wait_l4s14, l4s14, wait_l4s15, l4s15,
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wait_l4s16, l4s16, wait_l4s17, l4s17, wait_l4s18, l4s18, wait_l4s19, l4s19, wait_l4s20, l4s20,
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wait_new_line1, new_line1, wait_new_line2, new_line2, wait_new_line3, new_line3, wait_new_line4, new_line4,
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wait_renew );
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signal pr_state, nxt_state : state;
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signal one_usec, rst_int : STD_LOGIC := '0';
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signal counter : INTEGER RANGE 0 TO max_factor;
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SIGNAL lcd_data_int : STD_LOGIC_VECTOR (9 DOWNTO 0);
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signal str1, lcd_reg : lcd_matrix;
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BEGIN
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lcd_reg <= str1;
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str1 <=( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI,
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DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
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' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/',
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'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?',
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'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O' );
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-- str1 <= ( ' ',' ',' ',' ',' ','T','U',' ','C','h','e','m','n','i','t','z',' ',' ',' ',' ',
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-- ' ',' ',' ',' ',' ',' ',' ',' ','S','S','E',' ',' ',' ',' ',' ',' ',' ',' ',' ',
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-- ' ',' ','D','i','m','o',' ','P','e','p','e','l','y','a','s','h','e','v',' ',' ',
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-- ' ',' ',' ',' ',' ',' ',' ',' ','-','-','-',' ',' ',' ',' ',' ',' ',' ',' ',' ' );
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lcd_rw <= '0'; -- only writing to the LCD needed, lcd_data_int(8) is never used
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lcd_rs <= lcd_data_int(9);
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lcd_data <= lcd_data_int(7 downto 0);
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led(0) <= clk_400;
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--------------------------------------------------------------------------------------
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-- generates a signal with 1us period
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--------------------------------------------------------------------------------------
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one_sec_p: process(clk)
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VARIABLE temp : integer RANGE 0 TO one_usec_factor;
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begin
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IF clk'event AND clk='1' THEN
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IF rst_int='0' THEN
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temp := 0;
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one_usec <= '1'; -- because dalay_p counts on a positive transition
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else
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iF temp>=one_usec_factor THEN
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temp := 0;
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one_usec <= NOT one_usec;
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else
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temp := temp + 1;
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END if;
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END if;
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END IF;
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END process;
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--------------------------------------------------------------------------------------
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-- delays generetor
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--------------------------------------------------------------------------------------
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delay_p: process(clk)
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variable temp0 : integer RANGE 0 TO max_factor;
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VARIABLE flag : STD_LOGIC := '0';
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BEGIN
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IF clk'EVENT AND clk='1' THEN
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IF rst_int='0' THEN
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temp0 := 0;
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else
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IF one_usec='0' AND flag='1' THEN
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flag := '0';
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END IF;
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--the following part is executed only on a positive transition of one_usec
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IF one_usec='1' AND flag='0' THEN
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flag := '1';
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IF
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temp0>=max_factor THEN
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temp0 := 0;
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ELSE
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temp0 := temp0 + 1;
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end if;
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END if;
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END if;
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END if;
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counter <= temp0;
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END process;
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-------------------------------------------------------------------------------
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-- LCD enable signal generation
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-------------------------------------------------------------------------------
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lcd_en: process(clk)
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BEGIN
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IF clk'EVENT AND clk='1' THEN
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IF counter=1 THEN
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lcd_ena <= '1';
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ELSE
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lcd_ena <= '0';
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END IF;
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END IF;
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END process;
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---------------------------------------------------------------------------------
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-- MORE automat
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---------------------------------------------------------------------------------
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main_s_p: process(clk)
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begin
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if clk'event and clk='1' then
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IF rst='0' THEN
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pr_state <= init_start;
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else
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pr_state <= nxt_state;
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end if;
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END if;
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end process;
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main_c_p: process(pr_state,counter)
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begin
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case pr_state is
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WHEN init_start =>
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nxt_state <= wait_set1;
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rst_int <= '0';
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lcd_data_int <= (OTHERS => '0');
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WHEN wait_set1 =>
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IF counter>=init_factor THEN
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nxt_state <= set1;
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ELSE
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nxt_state <= wait_set1;
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END IF;
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lcd_data_int <= (OTHERS => '0');
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rst_int <= '1';
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WHEN set1 =>
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nxt_state <= wait_eset;
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rst_int <= '0';
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lcd_data_int <= ext_mode; -- goto extension mode
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WHEN wait_eset =>
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IF counter>=normal_factor THEN
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nxt_state <= eset;
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ELSE
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nxt_state <= wait_eset;
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END IF;
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lcd_data_int <= ext_mode;
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rst_int <= '1';
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WHEN eset =>
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nxt_state <= wait_set2;
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rst_int <= '0';
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lcd_data_int <= lines_4; -- 4 lines. 5x8 font, goto normal mode
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WHEN wait_set2 =>
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IF counter>=normal_factor THEN
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nxt_state <= set2;
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ELSE
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nxt_state <= wait_set2;
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END IF;
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lcd_data_int <= lines_4;
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rst_int <= '1';
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WHEN set2 =>
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nxt_state <= wait_lcd_on;
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rst_int <= '0';
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lcd_data_int <= data_8bit; -- 8 bit data
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WHEN wait_lcd_on =>
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IF counter>=normal_factor THEN
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nxt_state <= lcd_on;
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ELSE
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nxt_state <= wait_lcd_on;
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END IF;
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lcd_data_int <= data_8bit;
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rst_int <= '1';
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WHEN lcd_on =>
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nxt_state <= wait_lcd_clear;
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rst_int <= '0';
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lcd_data_int <= display_on; -- display on, cursor off, blinking off,
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WHEN wait_lcd_clear =>
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IF counter>=normal_factor THEN
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nxt_state <= lcd_clear;
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ELSE
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nxt_state <= wait_lcd_clear;
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END IF;
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lcd_data_int <= display_on;
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rst_int <= '1';
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WHEN lcd_clear =>
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nxt_state <= wait_lcd_entr;
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rst_int <= '0';
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lcd_data_int <= display_clear; -- clear display
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218 |
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WHEN wait_lcd_entr =>
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IF counter>=extended_factor THEN
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nxt_state <= lcd_entr;
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ELSE
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nxt_state <= wait_lcd_entr;
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END IF;
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lcd_data_int <= display_clear;
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225 |
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rst_int <= '1';
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WHEN lcd_entr =>
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nxt_state <= wait_l1s1;
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228 |
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rst_int <= '0';
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lcd_data_int <= entry_mode; -- goto entry mode, cursor moves right, shift off
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230 |
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WHEN wait_l1s1 =>
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IF counter>=normal_factor THEN
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nxt_state <= l1s1;
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ELSE
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nxt_state <= wait_l1s1;
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END IF;
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lcd_data_int <= entry_mode;
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237 |
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rst_int <= '1';
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-------------------------------------------------------------------------------
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-- line 1
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240 |
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-------------------------------------------------------------------------------
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241 |
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WHEN l1s1 =>
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nxt_state <= wait_l1s2;
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243 |
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rst_int <= '0';
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244 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(1));
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245 |
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WHEN wait_l1s2 =>
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246 |
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IF counter>=normal_factor THEN
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nxt_state <= l1s2;
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248 |
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ELSE
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249 |
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nxt_state <= wait_l1s2;
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250 |
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END IF;
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251 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(1));
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252 |
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rst_int <= '1';
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253 |
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WHEN l1s2 =>
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254 |
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nxt_state <= wait_l1s3;
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255 |
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rst_int <= '0';
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256 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(2));
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257 |
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WHEN wait_l1s3 =>
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258 |
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IF counter>=normal_factor THEN
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259 |
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nxt_state <= l1s3;
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260 |
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ELSE
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261 |
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nxt_state <= wait_l1s3;
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262 |
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END IF;
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263 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(2));
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264 |
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rst_int <= '1';
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265 |
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WHEN l1s3 =>
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266 |
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nxt_state <= wait_l1s4;
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267 |
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rst_int <= '0';
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268 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(3));
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269 |
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WHEN wait_l1s4 =>
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270 |
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IF counter>=normal_factor THEN
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271 |
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nxt_state <= l1s4;
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272 |
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ELSE
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273 |
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nxt_state <= wait_l1s4;
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274 |
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END IF;
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275 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(3));
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276 |
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rst_int <= '1';
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277 |
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WHEN l1s4 =>
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278 |
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nxt_state <= wait_l1s5;
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279 |
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rst_int <= '0';
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280 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(4));
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281 |
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WHEN wait_l1s5 =>
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282 |
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IF counter>=normal_factor THEN
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283 |
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nxt_state <= l1s5;
|
284 |
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ELSE
|
285 |
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nxt_state <= wait_l1s5;
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286 |
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END IF;
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287 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(4));
|
288 |
|
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rst_int <= '1';
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289 |
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WHEN l1s5 =>
|
290 |
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nxt_state <= wait_l1s6;
|
291 |
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rst_int <= '0';
|
292 |
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lcd_data_int <= '1' & '0' & char2std(lcd_reg(5));
|
293 |
|
|
WHEN wait_l1s6 =>
|
294 |
|
|
IF counter>=normal_factor THEN
|
295 |
|
|
nxt_state <= l1s6;
|
296 |
|
|
ELSE
|
297 |
|
|
nxt_state <= wait_l1s6;
|
298 |
|
|
END IF;
|
299 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(5));
|
300 |
|
|
rst_int <= '1';
|
301 |
|
|
WHEN l1s6 =>
|
302 |
|
|
nxt_state <= wait_l1s7;
|
303 |
|
|
rst_int <= '0';
|
304 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(6));
|
305 |
|
|
WHEN wait_l1s7 =>
|
306 |
|
|
IF counter>=normal_factor THEN
|
307 |
|
|
nxt_state <= l1s7;
|
308 |
|
|
ELSE
|
309 |
|
|
nxt_state <= wait_l1s7;
|
310 |
|
|
END IF;
|
311 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(6));
|
312 |
|
|
rst_int <= '1';
|
313 |
|
|
WHEN l1s7 =>
|
314 |
|
|
nxt_state <= wait_l1s8;
|
315 |
|
|
rst_int <= '0';
|
316 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(7));
|
317 |
|
|
WHEN wait_l1s8 =>
|
318 |
|
|
IF counter>=normal_factor THEN
|
319 |
|
|
nxt_state <= l1s8;
|
320 |
|
|
ELSE
|
321 |
|
|
nxt_state <= wait_l1s8;
|
322 |
|
|
END IF;
|
323 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(7));
|
324 |
|
|
rst_int <= '1';
|
325 |
|
|
WHEN l1s8 =>
|
326 |
|
|
nxt_state <= wait_l1s9;
|
327 |
|
|
rst_int <= '0';
|
328 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(8));
|
329 |
|
|
WHEN wait_l1s9 =>
|
330 |
|
|
IF counter>=normal_factor THEN
|
331 |
|
|
nxt_state <= l1s9;
|
332 |
|
|
ELSE
|
333 |
|
|
nxt_state <= wait_l1s9;
|
334 |
|
|
END IF;
|
335 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(8));
|
336 |
|
|
rst_int <= '1';
|
337 |
|
|
WHEN l1s9 =>
|
338 |
|
|
nxt_state <= wait_l1s10;
|
339 |
|
|
rst_int <= '0';
|
340 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(9));
|
341 |
|
|
WHEN wait_l1s10 =>
|
342 |
|
|
IF counter>=normal_factor THEN
|
343 |
|
|
nxt_state <= l1s10;
|
344 |
|
|
ELSE
|
345 |
|
|
nxt_state <= wait_l1s10;
|
346 |
|
|
END IF;
|
347 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(9));
|
348 |
|
|
rst_int <= '1';
|
349 |
|
|
WHEN l1s10 =>
|
350 |
|
|
nxt_state <= wait_l1s11;
|
351 |
|
|
rst_int <= '0';
|
352 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(10));
|
353 |
|
|
WHEN wait_l1s11 =>
|
354 |
|
|
IF counter>=normal_factor THEN
|
355 |
|
|
nxt_state <= l1s11;
|
356 |
|
|
ELSE
|
357 |
|
|
nxt_state <= wait_l1s11;
|
358 |
|
|
END IF;
|
359 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(10));
|
360 |
|
|
rst_int <= '1';
|
361 |
|
|
WHEN l1s11 =>
|
362 |
|
|
nxt_state <= wait_l1s12;
|
363 |
|
|
rst_int <= '0';
|
364 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(11));
|
365 |
|
|
WHEN wait_l1s12 =>
|
366 |
|
|
IF counter>=normal_factor THEN
|
367 |
|
|
nxt_state <= l1s12;
|
368 |
|
|
ELSE
|
369 |
|
|
nxt_state <= wait_l1s12;
|
370 |
|
|
END IF;
|
371 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(11));
|
372 |
|
|
rst_int <= '1';
|
373 |
|
|
WHEN l1s12 =>
|
374 |
|
|
nxt_state <= wait_l1s13;
|
375 |
|
|
rst_int <= '0';
|
376 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(12));
|
377 |
|
|
WHEN wait_l1s13 =>
|
378 |
|
|
IF counter>=normal_factor THEN
|
379 |
|
|
nxt_state <= l1s13;
|
380 |
|
|
ELSE
|
381 |
|
|
nxt_state <= wait_l1s13;
|
382 |
|
|
END IF;
|
383 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(12));
|
384 |
|
|
rst_int <= '1';
|
385 |
|
|
WHEN l1s13 =>
|
386 |
|
|
nxt_state <= wait_l1s14;
|
387 |
|
|
rst_int <= '0';
|
388 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(13));
|
389 |
|
|
WHEN wait_l1s14 =>
|
390 |
|
|
IF counter>=normal_factor THEN
|
391 |
|
|
nxt_state <= l1s14;
|
392 |
|
|
ELSE
|
393 |
|
|
nxt_state <= wait_l1s14;
|
394 |
|
|
END IF;
|
395 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(13));
|
396 |
|
|
rst_int <= '1';
|
397 |
|
|
WHEN l1s14 =>
|
398 |
|
|
nxt_state <= wait_l1s15;
|
399 |
|
|
rst_int <= '0';
|
400 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(14));
|
401 |
|
|
WHEN wait_l1s15 =>
|
402 |
|
|
IF counter>=normal_factor THEN
|
403 |
|
|
nxt_state <= l1s15;
|
404 |
|
|
ELSE
|
405 |
|
|
nxt_state <= wait_l1s15;
|
406 |
|
|
END IF;
|
407 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(14));
|
408 |
|
|
rst_int <= '1';
|
409 |
|
|
WHEN l1s15 =>
|
410 |
|
|
nxt_state <= wait_l1s16;
|
411 |
|
|
rst_int <= '0';
|
412 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(15));
|
413 |
|
|
WHEN wait_l1s16 =>
|
414 |
|
|
IF counter>=normal_factor THEN
|
415 |
|
|
nxt_state <= l1s16;
|
416 |
|
|
ELSE
|
417 |
|
|
nxt_state <= wait_l1s16;
|
418 |
|
|
END IF;
|
419 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(15));
|
420 |
|
|
rst_int <= '1';
|
421 |
|
|
WHEN l1s16 =>
|
422 |
|
|
nxt_state <= wait_l1s17;
|
423 |
|
|
rst_int <= '0';
|
424 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(16));
|
425 |
|
|
WHEN wait_l1s17 =>
|
426 |
|
|
IF counter>=normal_factor THEN
|
427 |
|
|
nxt_state <= l1s17;
|
428 |
|
|
ELSE
|
429 |
|
|
nxt_state <= wait_l1s17;
|
430 |
|
|
END IF;
|
431 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(16));
|
432 |
|
|
rst_int <= '1';
|
433 |
|
|
WHEN l1s17 =>
|
434 |
|
|
nxt_state <= wait_l1s18;
|
435 |
|
|
rst_int <= '0';
|
436 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(17));
|
437 |
|
|
WHEN wait_l1s18 =>
|
438 |
|
|
IF counter>=normal_factor THEN
|
439 |
|
|
nxt_state <= l1s18;
|
440 |
|
|
ELSE
|
441 |
|
|
nxt_state <= wait_l1s18;
|
442 |
|
|
END IF;
|
443 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(17));
|
444 |
|
|
rst_int <= '1';
|
445 |
|
|
WHEN l1s18 =>
|
446 |
|
|
nxt_state <= wait_l1s19;
|
447 |
|
|
rst_int <= '0';
|
448 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(18));
|
449 |
|
|
WHEN wait_l1s19 =>
|
450 |
|
|
IF counter>=normal_factor THEN
|
451 |
|
|
nxt_state <= l1s19;
|
452 |
|
|
ELSE
|
453 |
|
|
nxt_state <= wait_l1s19;
|
454 |
|
|
END IF;
|
455 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(18));
|
456 |
|
|
rst_int <= '1';
|
457 |
|
|
WHEN l1s19 =>
|
458 |
|
|
nxt_state <= wait_l1s20;
|
459 |
|
|
rst_int <= '0';
|
460 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(19));
|
461 |
|
|
WHEN wait_l1s20 =>
|
462 |
|
|
IF counter>=normal_factor THEN
|
463 |
|
|
nxt_state <= l1s20;
|
464 |
|
|
ELSE
|
465 |
|
|
nxt_state <= wait_l1s20;
|
466 |
|
|
END IF;
|
467 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(19));
|
468 |
|
|
rst_int <= '1';
|
469 |
|
|
WHEN l1s20 =>
|
470 |
|
|
nxt_state <= wait_new_line1;
|
471 |
|
|
rst_int <= '0';
|
472 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(20));
|
473 |
|
|
WHEN wait_new_line1 =>
|
474 |
|
|
IF counter>=normal_factor THEN
|
475 |
|
|
nxt_state <= new_line1;
|
476 |
|
|
ELSE
|
477 |
|
|
nxt_state <= wait_new_line1;
|
478 |
|
|
END IF;
|
479 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(20));
|
480 |
|
|
rst_int <= '1';
|
481 |
|
|
WHEN new_line1 =>
|
482 |
|
|
nxt_state <= wait_l2s1;
|
483 |
|
|
rst_int <= '0';
|
484 |
|
|
lcd_data_int <= "0010100000";
|
485 |
|
|
WHEN wait_l2s1 =>
|
486 |
|
|
IF counter>=normal_factor THEN
|
487 |
|
|
nxt_state <= l2s1;
|
488 |
|
|
ELSE
|
489 |
|
|
nxt_state <= wait_l2s1;
|
490 |
|
|
END IF;
|
491 |
|
|
lcd_data_int <= "0010100000";
|
492 |
|
|
rst_int <= '1';
|
493 |
|
|
-------------------------------------------------------------------------------
|
494 |
|
|
-- line 2
|
495 |
|
|
-------------------------------------------------------------------------------
|
496 |
|
|
WHEN l2s1 =>
|
497 |
|
|
nxt_state <= wait_l2s2;
|
498 |
|
|
rst_int <= '0';
|
499 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(21));
|
500 |
|
|
WHEN wait_l2s2 =>
|
501 |
|
|
IF counter>=normal_factor THEN
|
502 |
|
|
nxt_state <= l2s2;
|
503 |
|
|
ELSE
|
504 |
|
|
nxt_state <= wait_l2s2;
|
505 |
|
|
END IF;
|
506 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(21));
|
507 |
|
|
rst_int <= '1';
|
508 |
|
|
WHEN l2s2 =>
|
509 |
|
|
nxt_state <= wait_l2s3;
|
510 |
|
|
rst_int <= '0';
|
511 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(22));
|
512 |
|
|
WHEN wait_l2s3 =>
|
513 |
|
|
IF counter>=normal_factor THEN
|
514 |
|
|
nxt_state <= l2s3;
|
515 |
|
|
ELSE
|
516 |
|
|
nxt_state <= wait_l2s3;
|
517 |
|
|
END IF;
|
518 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(22));
|
519 |
|
|
rst_int <= '1';
|
520 |
|
|
WHEN l2s3 =>
|
521 |
|
|
nxt_state <= wait_l2s4;
|
522 |
|
|
rst_int <= '0';
|
523 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(23));
|
524 |
|
|
WHEN wait_l2s4 =>
|
525 |
|
|
IF counter>=normal_factor THEN
|
526 |
|
|
nxt_state <= l2s4;
|
527 |
|
|
ELSE
|
528 |
|
|
nxt_state <= wait_l2s4;
|
529 |
|
|
END IF;
|
530 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(23));
|
531 |
|
|
rst_int <= '1';
|
532 |
|
|
WHEN l2s4 =>
|
533 |
|
|
nxt_state <= wait_l2s5;
|
534 |
|
|
rst_int <= '0';
|
535 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(24));
|
536 |
|
|
WHEN wait_l2s5 =>
|
537 |
|
|
IF counter>=normal_factor THEN
|
538 |
|
|
nxt_state <= l2s5;
|
539 |
|
|
ELSE
|
540 |
|
|
nxt_state <= wait_l2s5;
|
541 |
|
|
END IF;
|
542 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(24));
|
543 |
|
|
rst_int <= '1';
|
544 |
|
|
WHEN l2s5 =>
|
545 |
|
|
nxt_state <= wait_l2s6;
|
546 |
|
|
rst_int <= '0';
|
547 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(25));
|
548 |
|
|
WHEN wait_l2s6 =>
|
549 |
|
|
IF counter>=normal_factor THEN
|
550 |
|
|
nxt_state <= l2s6;
|
551 |
|
|
ELSE
|
552 |
|
|
nxt_state <= wait_l2s6;
|
553 |
|
|
END IF;
|
554 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(25));
|
555 |
|
|
rst_int <= '1';
|
556 |
|
|
WHEN l2s6 =>
|
557 |
|
|
nxt_state <= wait_l2s7;
|
558 |
|
|
rst_int <= '0';
|
559 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(26));
|
560 |
|
|
WHEN wait_l2s7 =>
|
561 |
|
|
IF counter>=normal_factor THEN
|
562 |
|
|
nxt_state <= l2s7;
|
563 |
|
|
ELSE
|
564 |
|
|
nxt_state <= wait_l2s7;
|
565 |
|
|
END IF;
|
566 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(26));
|
567 |
|
|
rst_int <= '1';
|
568 |
|
|
WHEN l2s7 =>
|
569 |
|
|
nxt_state <= wait_l2s8;
|
570 |
|
|
rst_int <= '0';
|
571 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(27));
|
572 |
|
|
WHEN wait_l2s8 =>
|
573 |
|
|
IF counter>=normal_factor THEN
|
574 |
|
|
nxt_state <= l2s8;
|
575 |
|
|
ELSE
|
576 |
|
|
nxt_state <= wait_l2s8;
|
577 |
|
|
END IF;
|
578 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(27));
|
579 |
|
|
rst_int <= '1';
|
580 |
|
|
WHEN l2s8 =>
|
581 |
|
|
nxt_state <= wait_l2s9;
|
582 |
|
|
rst_int <= '0';
|
583 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(28));
|
584 |
|
|
WHEN wait_l2s9 =>
|
585 |
|
|
IF counter>=normal_factor THEN
|
586 |
|
|
nxt_state <= l2s9;
|
587 |
|
|
ELSE
|
588 |
|
|
nxt_state <= wait_l2s9;
|
589 |
|
|
END IF;
|
590 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(28));
|
591 |
|
|
rst_int <= '1';
|
592 |
|
|
WHEN l2s9 =>
|
593 |
|
|
nxt_state <= wait_l2s10;
|
594 |
|
|
rst_int <= '0';
|
595 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(29));
|
596 |
|
|
WHEN wait_l2s10 =>
|
597 |
|
|
IF counter>=normal_factor THEN
|
598 |
|
|
nxt_state <= l2s10;
|
599 |
|
|
ELSE
|
600 |
|
|
nxt_state <= wait_l2s10;
|
601 |
|
|
END IF;
|
602 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(29));
|
603 |
|
|
rst_int <= '1';
|
604 |
|
|
WHEN l2s10 =>
|
605 |
|
|
nxt_state <= wait_l2s11;
|
606 |
|
|
rst_int <= '0';
|
607 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(30));
|
608 |
|
|
WHEN wait_l2s11 =>
|
609 |
|
|
IF counter>=normal_factor THEN
|
610 |
|
|
nxt_state <= l2s11;
|
611 |
|
|
ELSE
|
612 |
|
|
nxt_state <= wait_l2s11;
|
613 |
|
|
END IF;
|
614 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(30));
|
615 |
|
|
rst_int <= '1';
|
616 |
|
|
WHEN l2s11 =>
|
617 |
|
|
nxt_state <= wait_l2s12;
|
618 |
|
|
rst_int <= '0';
|
619 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(31));
|
620 |
|
|
WHEN wait_l2s12 =>
|
621 |
|
|
IF counter>=normal_factor THEN
|
622 |
|
|
nxt_state <= l2s12;
|
623 |
|
|
ELSE
|
624 |
|
|
nxt_state <= wait_l2s12;
|
625 |
|
|
END IF;
|
626 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(31));
|
627 |
|
|
rst_int <= '1';
|
628 |
|
|
WHEN l2s12 =>
|
629 |
|
|
nxt_state <= wait_l2s13;
|
630 |
|
|
rst_int <= '0';
|
631 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(32));
|
632 |
|
|
WHEN wait_l2s13 =>
|
633 |
|
|
IF counter>=normal_factor THEN
|
634 |
|
|
nxt_state <= l2s13;
|
635 |
|
|
ELSE
|
636 |
|
|
nxt_state <= wait_l2s13;
|
637 |
|
|
END IF;
|
638 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(32));
|
639 |
|
|
rst_int <= '1';
|
640 |
|
|
WHEN l2s13 =>
|
641 |
|
|
nxt_state <= wait_l2s14;
|
642 |
|
|
rst_int <= '0';
|
643 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(33));
|
644 |
|
|
WHEN wait_l2s14 =>
|
645 |
|
|
IF counter>=normal_factor THEN
|
646 |
|
|
nxt_state <= l2s14;
|
647 |
|
|
ELSE
|
648 |
|
|
nxt_state <= wait_l2s14;
|
649 |
|
|
END IF;
|
650 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(33));
|
651 |
|
|
rst_int <= '1';
|
652 |
|
|
WHEN l2s14 =>
|
653 |
|
|
nxt_state <= wait_l2s15;
|
654 |
|
|
rst_int <= '0';
|
655 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(34));
|
656 |
|
|
WHEN wait_l2s15 =>
|
657 |
|
|
IF counter>=normal_factor THEN
|
658 |
|
|
nxt_state <= l2s15;
|
659 |
|
|
ELSE
|
660 |
|
|
nxt_state <= wait_l2s15;
|
661 |
|
|
END IF;
|
662 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(34));
|
663 |
|
|
rst_int <= '1';
|
664 |
|
|
WHEN l2s15 =>
|
665 |
|
|
nxt_state <= wait_l2s16;
|
666 |
|
|
rst_int <= '0';
|
667 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(35));
|
668 |
|
|
WHEN wait_l2s16 =>
|
669 |
|
|
IF counter>=normal_factor THEN
|
670 |
|
|
nxt_state <= l2s16;
|
671 |
|
|
ELSE
|
672 |
|
|
nxt_state <= wait_l2s16;
|
673 |
|
|
END IF;
|
674 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(35));
|
675 |
|
|
rst_int <= '1';
|
676 |
|
|
WHEN l2s16 =>
|
677 |
|
|
nxt_state <= wait_l2s17;
|
678 |
|
|
rst_int <= '0';
|
679 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(36));
|
680 |
|
|
WHEN wait_l2s17 =>
|
681 |
|
|
IF counter>=normal_factor THEN
|
682 |
|
|
nxt_state <= l2s17;
|
683 |
|
|
ELSE
|
684 |
|
|
nxt_state <= wait_l2s17;
|
685 |
|
|
END IF;
|
686 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(36));
|
687 |
|
|
rst_int <= '1';
|
688 |
|
|
WHEN l2s17 =>
|
689 |
|
|
nxt_state <= wait_l2s18;
|
690 |
|
|
rst_int <= '0';
|
691 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(37));
|
692 |
|
|
WHEN wait_l2s18 =>
|
693 |
|
|
IF counter>=normal_factor THEN
|
694 |
|
|
nxt_state <= l2s18;
|
695 |
|
|
ELSE
|
696 |
|
|
nxt_state <= wait_l2s18;
|
697 |
|
|
END IF;
|
698 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(37));
|
699 |
|
|
rst_int <= '1';
|
700 |
|
|
WHEN l2s18 =>
|
701 |
|
|
nxt_state <= wait_l2s19;
|
702 |
|
|
rst_int <= '0';
|
703 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(38));
|
704 |
|
|
WHEN wait_l2s19 =>
|
705 |
|
|
IF counter>=normal_factor THEN
|
706 |
|
|
nxt_state <= l2s19;
|
707 |
|
|
ELSE
|
708 |
|
|
nxt_state <= wait_l2s19;
|
709 |
|
|
END IF;
|
710 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(38));
|
711 |
|
|
rst_int <= '1';
|
712 |
|
|
WHEN l2s19 =>
|
713 |
|
|
nxt_state <= wait_l2s20;
|
714 |
|
|
rst_int <= '0';
|
715 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(39));
|
716 |
|
|
WHEN wait_l2s20 =>
|
717 |
|
|
IF counter>=normal_factor THEN
|
718 |
|
|
nxt_state <= l2s20;
|
719 |
|
|
ELSE
|
720 |
|
|
nxt_state <= wait_l2s20;
|
721 |
|
|
END IF;
|
722 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(39));
|
723 |
|
|
rst_int <= '1';
|
724 |
|
|
WHEN l2s20 =>
|
725 |
|
|
nxt_state <= wait_new_line2;
|
726 |
|
|
rst_int <= '0';
|
727 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(40));
|
728 |
|
|
WHEN wait_new_line2 =>
|
729 |
|
|
IF counter>=normal_factor THEN
|
730 |
|
|
nxt_state <= new_line2;
|
731 |
|
|
ELSE
|
732 |
|
|
nxt_state <= wait_new_line2;
|
733 |
|
|
END IF;
|
734 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(40));
|
735 |
|
|
rst_int <= '1';
|
736 |
|
|
WHEN new_line2 =>
|
737 |
|
|
nxt_state <= wait_l3s1;
|
738 |
|
|
rst_int <= '0';
|
739 |
|
|
lcd_data_int <= "0011000000";
|
740 |
|
|
WHEN wait_l3s1 =>
|
741 |
|
|
IF counter>=normal_factor THEN
|
742 |
|
|
nxt_state <= l3s1;
|
743 |
|
|
ELSE
|
744 |
|
|
nxt_state <= wait_l3s1;
|
745 |
|
|
END IF;
|
746 |
|
|
lcd_data_int <= "0011000000";
|
747 |
|
|
rst_int <= '1';
|
748 |
|
|
|
749 |
|
|
-------------------------------------------------------------------------------
|
750 |
|
|
-- line 3
|
751 |
|
|
-------------------------------------------------------------------------------
|
752 |
|
|
WHEN l3s1 =>
|
753 |
|
|
nxt_state <= wait_l3s2;
|
754 |
|
|
rst_int <= '0';
|
755 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(41));
|
756 |
|
|
WHEN wait_l3s2 =>
|
757 |
|
|
IF counter>=normal_factor THEN
|
758 |
|
|
nxt_state <= l3s2;
|
759 |
|
|
ELSE
|
760 |
|
|
nxt_state <= wait_l3s2;
|
761 |
|
|
END IF;
|
762 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(41));
|
763 |
|
|
rst_int <= '1';
|
764 |
|
|
WHEN l3s2 =>
|
765 |
|
|
nxt_state <= wait_l3s3;
|
766 |
|
|
rst_int <= '0';
|
767 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(42));
|
768 |
|
|
WHEN wait_l3s3 =>
|
769 |
|
|
IF counter>=normal_factor THEN
|
770 |
|
|
nxt_state <= l3s3;
|
771 |
|
|
ELSE
|
772 |
|
|
nxt_state <= wait_l3s3;
|
773 |
|
|
END IF;
|
774 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(42));
|
775 |
|
|
rst_int <= '1';
|
776 |
|
|
WHEN l3s3 =>
|
777 |
|
|
nxt_state <= wait_l3s4;
|
778 |
|
|
rst_int <= '0';
|
779 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(43));
|
780 |
|
|
WHEN wait_l3s4 =>
|
781 |
|
|
IF counter>=normal_factor THEN
|
782 |
|
|
nxt_state <= l3s4;
|
783 |
|
|
ELSE
|
784 |
|
|
nxt_state <= wait_l3s4;
|
785 |
|
|
END IF;
|
786 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(43));
|
787 |
|
|
rst_int <= '1';
|
788 |
|
|
WHEN l3s4 =>
|
789 |
|
|
nxt_state <= wait_l3s5;
|
790 |
|
|
rst_int <= '0';
|
791 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(44));
|
792 |
|
|
WHEN wait_l3s5 =>
|
793 |
|
|
IF counter>=normal_factor THEN
|
794 |
|
|
nxt_state <= l3s5;
|
795 |
|
|
ELSE
|
796 |
|
|
nxt_state <= wait_l3s5;
|
797 |
|
|
END IF;
|
798 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(44));
|
799 |
|
|
rst_int <= '1';
|
800 |
|
|
WHEN l3s5 =>
|
801 |
|
|
nxt_state <= wait_l3s6;
|
802 |
|
|
rst_int <= '0';
|
803 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(45));
|
804 |
|
|
WHEN wait_l3s6 =>
|
805 |
|
|
IF counter>=normal_factor THEN
|
806 |
|
|
nxt_state <= l3s6;
|
807 |
|
|
ELSE
|
808 |
|
|
nxt_state <= wait_l3s6;
|
809 |
|
|
END IF;
|
810 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(45));
|
811 |
|
|
rst_int <= '1';
|
812 |
|
|
WHEN l3s6 =>
|
813 |
|
|
nxt_state <= wait_l3s7;
|
814 |
|
|
rst_int <= '0';
|
815 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(46));
|
816 |
|
|
WHEN wait_l3s7 =>
|
817 |
|
|
IF counter>=normal_factor THEN
|
818 |
|
|
nxt_state <= l3s7;
|
819 |
|
|
ELSE
|
820 |
|
|
nxt_state <= wait_l3s7;
|
821 |
|
|
END IF;
|
822 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(46));
|
823 |
|
|
rst_int <= '1';
|
824 |
|
|
WHEN l3s7 =>
|
825 |
|
|
nxt_state <= wait_l3s8;
|
826 |
|
|
rst_int <= '0';
|
827 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(47));
|
828 |
|
|
WHEN wait_l3s8 =>
|
829 |
|
|
IF counter>=normal_factor THEN
|
830 |
|
|
nxt_state <= l3s8;
|
831 |
|
|
ELSE
|
832 |
|
|
nxt_state <= wait_l3s8;
|
833 |
|
|
END IF;
|
834 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(47));
|
835 |
|
|
rst_int <= '1';
|
836 |
|
|
WHEN l3s8 =>
|
837 |
|
|
nxt_state <= wait_l3s9;
|
838 |
|
|
rst_int <= '0';
|
839 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(48));
|
840 |
|
|
WHEN wait_l3s9 =>
|
841 |
|
|
IF counter>=normal_factor THEN
|
842 |
|
|
nxt_state <= l3s9;
|
843 |
|
|
ELSE
|
844 |
|
|
nxt_state <= wait_l3s9;
|
845 |
|
|
END IF;
|
846 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(48));
|
847 |
|
|
rst_int <= '1';
|
848 |
|
|
WHEN l3s9 =>
|
849 |
|
|
nxt_state <= wait_l3s10;
|
850 |
|
|
rst_int <= '0';
|
851 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(49));
|
852 |
|
|
WHEN wait_l3s10 =>
|
853 |
|
|
IF counter>=normal_factor THEN
|
854 |
|
|
nxt_state <= l3s10;
|
855 |
|
|
ELSE
|
856 |
|
|
nxt_state <= wait_l3s10;
|
857 |
|
|
END IF;
|
858 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(49));
|
859 |
|
|
rst_int <= '1';
|
860 |
|
|
WHEN l3s10 =>
|
861 |
|
|
nxt_state <= wait_l3s11;
|
862 |
|
|
rst_int <= '0';
|
863 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(50));
|
864 |
|
|
WHEN wait_l3s11 =>
|
865 |
|
|
IF counter>=normal_factor THEN
|
866 |
|
|
nxt_state <= l3s11;
|
867 |
|
|
ELSE
|
868 |
|
|
nxt_state <= wait_l3s11;
|
869 |
|
|
END IF;
|
870 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(50));
|
871 |
|
|
rst_int <= '1';
|
872 |
|
|
WHEN l3s11 =>
|
873 |
|
|
nxt_state <= wait_l3s12;
|
874 |
|
|
rst_int <= '0';
|
875 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(51));
|
876 |
|
|
WHEN wait_l3s12 =>
|
877 |
|
|
IF counter>=normal_factor THEN
|
878 |
|
|
nxt_state <= l3s12;
|
879 |
|
|
ELSE
|
880 |
|
|
nxt_state <= wait_l3s12;
|
881 |
|
|
END IF;
|
882 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(51));
|
883 |
|
|
rst_int <= '1';
|
884 |
|
|
WHEN l3s12 =>
|
885 |
|
|
nxt_state <= wait_l3s13;
|
886 |
|
|
rst_int <= '0';
|
887 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(52));
|
888 |
|
|
WHEN wait_l3s13 =>
|
889 |
|
|
IF counter>=normal_factor THEN
|
890 |
|
|
nxt_state <= l3s13;
|
891 |
|
|
ELSE
|
892 |
|
|
nxt_state <= wait_l3s13;
|
893 |
|
|
END IF;
|
894 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(52));
|
895 |
|
|
rst_int <= '1';
|
896 |
|
|
WHEN l3s13 =>
|
897 |
|
|
nxt_state <= wait_l3s14;
|
898 |
|
|
rst_int <= '0';
|
899 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(53));
|
900 |
|
|
WHEN wait_l3s14 =>
|
901 |
|
|
IF counter>=normal_factor THEN
|
902 |
|
|
nxt_state <= l3s14;
|
903 |
|
|
ELSE
|
904 |
|
|
nxt_state <= wait_l3s14;
|
905 |
|
|
END IF;
|
906 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(53));
|
907 |
|
|
rst_int <= '1';
|
908 |
|
|
WHEN l3s14 =>
|
909 |
|
|
nxt_state <= wait_l3s15;
|
910 |
|
|
rst_int <= '0';
|
911 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(54));
|
912 |
|
|
WHEN wait_l3s15 =>
|
913 |
|
|
IF counter>=normal_factor THEN
|
914 |
|
|
nxt_state <= l3s15;
|
915 |
|
|
ELSE
|
916 |
|
|
nxt_state <= wait_l3s15;
|
917 |
|
|
END IF;
|
918 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(54));
|
919 |
|
|
rst_int <= '1';
|
920 |
|
|
WHEN l3s15 =>
|
921 |
|
|
nxt_state <= wait_l3s16;
|
922 |
|
|
rst_int <= '0';
|
923 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(55));
|
924 |
|
|
WHEN wait_l3s16 =>
|
925 |
|
|
IF counter>=normal_factor THEN
|
926 |
|
|
nxt_state <= l3s16;
|
927 |
|
|
ELSE
|
928 |
|
|
nxt_state <= wait_l3s16;
|
929 |
|
|
END IF;
|
930 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(55));
|
931 |
|
|
rst_int <= '1';
|
932 |
|
|
WHEN l3s16 =>
|
933 |
|
|
nxt_state <= wait_l3s17;
|
934 |
|
|
rst_int <= '0';
|
935 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(56));
|
936 |
|
|
WHEN wait_l3s17 =>
|
937 |
|
|
IF counter>=normal_factor THEN
|
938 |
|
|
nxt_state <= l3s17;
|
939 |
|
|
ELSE
|
940 |
|
|
nxt_state <= wait_l3s17;
|
941 |
|
|
END IF;
|
942 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(56));
|
943 |
|
|
rst_int <= '1';
|
944 |
|
|
WHEN l3s17 =>
|
945 |
|
|
nxt_state <= wait_l3s18;
|
946 |
|
|
rst_int <= '0';
|
947 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(57));
|
948 |
|
|
WHEN wait_l3s18 =>
|
949 |
|
|
IF counter>=normal_factor THEN
|
950 |
|
|
nxt_state <= l3s18;
|
951 |
|
|
ELSE
|
952 |
|
|
nxt_state <= wait_l3s18;
|
953 |
|
|
END IF;
|
954 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(57));
|
955 |
|
|
rst_int <= '1';
|
956 |
|
|
WHEN l3s18 =>
|
957 |
|
|
nxt_state <= wait_l3s19;
|
958 |
|
|
rst_int <= '0';
|
959 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(58));
|
960 |
|
|
WHEN wait_l3s19 =>
|
961 |
|
|
IF counter>=normal_factor THEN
|
962 |
|
|
nxt_state <= l3s19;
|
963 |
|
|
ELSE
|
964 |
|
|
nxt_state <= wait_l3s19;
|
965 |
|
|
END IF;
|
966 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(58));
|
967 |
|
|
rst_int <= '1';
|
968 |
|
|
WHEN l3s19 =>
|
969 |
|
|
nxt_state <= wait_l3s20;
|
970 |
|
|
rst_int <= '0';
|
971 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(59));
|
972 |
|
|
WHEN wait_l3s20 =>
|
973 |
|
|
IF counter>=normal_factor THEN
|
974 |
|
|
nxt_state <= l3s20;
|
975 |
|
|
ELSE
|
976 |
|
|
nxt_state <= wait_l3s20;
|
977 |
|
|
END IF;
|
978 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(59));
|
979 |
|
|
rst_int <= '1';
|
980 |
|
|
WHEN l3s20 =>
|
981 |
|
|
nxt_state <= wait_new_line3;
|
982 |
|
|
rst_int <= '0';
|
983 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(60));
|
984 |
|
|
WHEN wait_new_line3 =>
|
985 |
|
|
IF counter>=normal_factor THEN
|
986 |
|
|
nxt_state <= new_line3;
|
987 |
|
|
ELSE
|
988 |
|
|
nxt_state <= wait_new_line3;
|
989 |
|
|
END IF;
|
990 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(60));
|
991 |
|
|
rst_int <= '1';
|
992 |
|
|
WHEN new_line3 =>
|
993 |
|
|
nxt_state <= wait_l4s1;
|
994 |
|
|
rst_int <= '0';
|
995 |
|
|
lcd_data_int <= "0011100000";
|
996 |
|
|
WHEN wait_l4s1 =>
|
997 |
|
|
IF counter>=normal_factor THEN
|
998 |
|
|
nxt_state <= l4s1;
|
999 |
|
|
ELSE
|
1000 |
|
|
nxt_state <= wait_l4s1;
|
1001 |
|
|
END IF;
|
1002 |
|
|
lcd_data_int <= "0011100000";
|
1003 |
|
|
rst_int <= '1';
|
1004 |
|
|
|
1005 |
|
|
-------------------------------------------------------------------------------
|
1006 |
|
|
-- line 4
|
1007 |
|
|
-------------------------------------------------------------------------------
|
1008 |
|
|
WHEN l4s1 =>
|
1009 |
|
|
nxt_state <= wait_l4s2;
|
1010 |
|
|
rst_int <= '0';
|
1011 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(61));
|
1012 |
|
|
WHEN wait_l4s2 =>
|
1013 |
|
|
IF counter>=normal_factor THEN
|
1014 |
|
|
nxt_state <= l4s2;
|
1015 |
|
|
ELSE
|
1016 |
|
|
nxt_state <= wait_l4s2;
|
1017 |
|
|
END IF;
|
1018 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(61));
|
1019 |
|
|
rst_int <= '1';
|
1020 |
|
|
WHEN l4s2 =>
|
1021 |
|
|
nxt_state <= wait_l4s3;
|
1022 |
|
|
rst_int <= '0';
|
1023 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(62));
|
1024 |
|
|
WHEN wait_l4s3 =>
|
1025 |
|
|
IF counter>=normal_factor THEN
|
1026 |
|
|
nxt_state <= l4s3;
|
1027 |
|
|
ELSE
|
1028 |
|
|
nxt_state <= wait_l4s3;
|
1029 |
|
|
END IF;
|
1030 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(62));
|
1031 |
|
|
rst_int <= '1';
|
1032 |
|
|
WHEN l4s3 =>
|
1033 |
|
|
nxt_state <= wait_l4s4;
|
1034 |
|
|
rst_int <= '0';
|
1035 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(63));
|
1036 |
|
|
WHEN wait_l4s4 =>
|
1037 |
|
|
IF counter>=normal_factor THEN
|
1038 |
|
|
nxt_state <= l4s4;
|
1039 |
|
|
ELSE
|
1040 |
|
|
nxt_state <= wait_l4s4;
|
1041 |
|
|
END IF;
|
1042 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(63));
|
1043 |
|
|
rst_int <= '1';
|
1044 |
|
|
WHEN l4s4 =>
|
1045 |
|
|
nxt_state <= wait_l4s5;
|
1046 |
|
|
rst_int <= '0';
|
1047 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(64));
|
1048 |
|
|
WHEN wait_l4s5 =>
|
1049 |
|
|
IF counter>=normal_factor THEN
|
1050 |
|
|
nxt_state <= l4s5;
|
1051 |
|
|
ELSE
|
1052 |
|
|
nxt_state <= wait_l4s5;
|
1053 |
|
|
END IF;
|
1054 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(64));
|
1055 |
|
|
rst_int <= '1';
|
1056 |
|
|
WHEN l4s5 =>
|
1057 |
|
|
nxt_state <= wait_l4s6;
|
1058 |
|
|
rst_int <= '0';
|
1059 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(65));
|
1060 |
|
|
WHEN wait_l4s6 =>
|
1061 |
|
|
IF counter>=normal_factor THEN
|
1062 |
|
|
nxt_state <= l4s6;
|
1063 |
|
|
ELSE
|
1064 |
|
|
nxt_state <= wait_l4s6;
|
1065 |
|
|
END IF;
|
1066 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(65));
|
1067 |
|
|
rst_int <= '1';
|
1068 |
|
|
WHEN l4s6 =>
|
1069 |
|
|
nxt_state <= wait_l4s7;
|
1070 |
|
|
rst_int <= '0';
|
1071 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(66));
|
1072 |
|
|
WHEN wait_l4s7 =>
|
1073 |
|
|
IF counter>=normal_factor THEN
|
1074 |
|
|
nxt_state <= l4s7;
|
1075 |
|
|
ELSE
|
1076 |
|
|
nxt_state <= wait_l4s7;
|
1077 |
|
|
END IF;
|
1078 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(66));
|
1079 |
|
|
rst_int <= '1';
|
1080 |
|
|
WHEN l4s7 =>
|
1081 |
|
|
nxt_state <= wait_l4s8;
|
1082 |
|
|
rst_int <= '0';
|
1083 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(67));
|
1084 |
|
|
WHEN wait_l4s8 =>
|
1085 |
|
|
IF counter>=normal_factor THEN
|
1086 |
|
|
nxt_state <= l4s8;
|
1087 |
|
|
ELSE
|
1088 |
|
|
nxt_state <= wait_l4s8;
|
1089 |
|
|
END IF;
|
1090 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(67));
|
1091 |
|
|
rst_int <= '1';
|
1092 |
|
|
WHEN l4s8 =>
|
1093 |
|
|
nxt_state <= wait_l4s9;
|
1094 |
|
|
rst_int <= '0';
|
1095 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(68));
|
1096 |
|
|
WHEN wait_l4s9 =>
|
1097 |
|
|
IF counter>=normal_factor THEN
|
1098 |
|
|
nxt_state <= l4s9;
|
1099 |
|
|
ELSE
|
1100 |
|
|
nxt_state <= wait_l4s9;
|
1101 |
|
|
END IF;
|
1102 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(68));
|
1103 |
|
|
rst_int <= '1';
|
1104 |
|
|
WHEN l4s9 =>
|
1105 |
|
|
nxt_state <= wait_l4s10;
|
1106 |
|
|
rst_int <= '0';
|
1107 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(69));
|
1108 |
|
|
WHEN wait_l4s10 =>
|
1109 |
|
|
IF counter>=normal_factor THEN
|
1110 |
|
|
nxt_state <= l4s10;
|
1111 |
|
|
ELSE
|
1112 |
|
|
nxt_state <= wait_l4s10;
|
1113 |
|
|
END IF;
|
1114 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(69));
|
1115 |
|
|
rst_int <= '1';
|
1116 |
|
|
WHEN l4s10 =>
|
1117 |
|
|
nxt_state <= wait_l4s11;
|
1118 |
|
|
rst_int <= '0';
|
1119 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(70));
|
1120 |
|
|
WHEN wait_l4s11 =>
|
1121 |
|
|
IF counter>=normal_factor THEN
|
1122 |
|
|
nxt_state <= l4s11;
|
1123 |
|
|
ELSE
|
1124 |
|
|
nxt_state <= wait_l4s11;
|
1125 |
|
|
END IF;
|
1126 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(70));
|
1127 |
|
|
rst_int <= '1';
|
1128 |
|
|
WHEN l4s11 =>
|
1129 |
|
|
nxt_state <= wait_l4s12;
|
1130 |
|
|
rst_int <= '0';
|
1131 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(71));
|
1132 |
|
|
WHEN wait_l4s12 =>
|
1133 |
|
|
IF counter>=normal_factor THEN
|
1134 |
|
|
nxt_state <= l4s12;
|
1135 |
|
|
ELSE
|
1136 |
|
|
nxt_state <= wait_l4s12;
|
1137 |
|
|
END IF;
|
1138 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(71));
|
1139 |
|
|
rst_int <= '1';
|
1140 |
|
|
WHEN l4s12 =>
|
1141 |
|
|
nxt_state <= wait_l4s13;
|
1142 |
|
|
rst_int <= '0';
|
1143 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(72));
|
1144 |
|
|
WHEN wait_l4s13 =>
|
1145 |
|
|
IF counter>=normal_factor THEN
|
1146 |
|
|
nxt_state <= l4s13;
|
1147 |
|
|
ELSE
|
1148 |
|
|
nxt_state <= wait_l4s13;
|
1149 |
|
|
END IF;
|
1150 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(72));
|
1151 |
|
|
rst_int <= '1';
|
1152 |
|
|
WHEN l4s13 =>
|
1153 |
|
|
nxt_state <= wait_l4s14;
|
1154 |
|
|
rst_int <= '0';
|
1155 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(73));
|
1156 |
|
|
WHEN wait_l4s14 =>
|
1157 |
|
|
IF counter>=normal_factor THEN
|
1158 |
|
|
nxt_state <= l4s14;
|
1159 |
|
|
ELSE
|
1160 |
|
|
nxt_state <= wait_l4s14;
|
1161 |
|
|
END IF;
|
1162 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(73));
|
1163 |
|
|
rst_int <= '1';
|
1164 |
|
|
WHEN l4s14 =>
|
1165 |
|
|
nxt_state <= wait_l4s15;
|
1166 |
|
|
rst_int <= '0';
|
1167 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(74));
|
1168 |
|
|
WHEN wait_l4s15 =>
|
1169 |
|
|
IF counter>=normal_factor THEN
|
1170 |
|
|
nxt_state <= l4s15;
|
1171 |
|
|
ELSE
|
1172 |
|
|
nxt_state <= wait_l4s15;
|
1173 |
|
|
END IF;
|
1174 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(74));
|
1175 |
|
|
rst_int <= '1';
|
1176 |
|
|
WHEN l4s15 =>
|
1177 |
|
|
nxt_state <= wait_l4s16;
|
1178 |
|
|
rst_int <= '0';
|
1179 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(75));
|
1180 |
|
|
WHEN wait_l4s16 =>
|
1181 |
|
|
IF counter>=normal_factor THEN
|
1182 |
|
|
nxt_state <= l4s16;
|
1183 |
|
|
ELSE
|
1184 |
|
|
nxt_state <= wait_l4s16;
|
1185 |
|
|
END IF;
|
1186 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(75));
|
1187 |
|
|
rst_int <= '1';
|
1188 |
|
|
WHEN l4s16 =>
|
1189 |
|
|
nxt_state <= wait_l4s17;
|
1190 |
|
|
rst_int <= '0';
|
1191 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(76));
|
1192 |
|
|
WHEN wait_l4s17 =>
|
1193 |
|
|
IF counter>=normal_factor THEN
|
1194 |
|
|
nxt_state <= l4s17;
|
1195 |
|
|
ELSE
|
1196 |
|
|
nxt_state <= wait_l4s17;
|
1197 |
|
|
END IF;
|
1198 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(76));
|
1199 |
|
|
rst_int <= '1';
|
1200 |
|
|
WHEN l4s17 =>
|
1201 |
|
|
nxt_state <= wait_l4s18;
|
1202 |
|
|
rst_int <= '0';
|
1203 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(77));
|
1204 |
|
|
WHEN wait_l4s18 =>
|
1205 |
|
|
IF counter>=normal_factor THEN
|
1206 |
|
|
nxt_state <= l4s18;
|
1207 |
|
|
ELSE
|
1208 |
|
|
nxt_state <= wait_l4s18;
|
1209 |
|
|
END IF;
|
1210 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(77));
|
1211 |
|
|
rst_int <= '1';
|
1212 |
|
|
WHEN l4s18 =>
|
1213 |
|
|
nxt_state <= wait_l4s19;
|
1214 |
|
|
rst_int <= '0';
|
1215 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(78));
|
1216 |
|
|
WHEN wait_l4s19 =>
|
1217 |
|
|
IF counter>=normal_factor THEN
|
1218 |
|
|
nxt_state <= l4s19;
|
1219 |
|
|
ELSE
|
1220 |
|
|
nxt_state <= wait_l4s19;
|
1221 |
|
|
END IF;
|
1222 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(78));
|
1223 |
|
|
rst_int <= '1';
|
1224 |
|
|
WHEN l4s19 =>
|
1225 |
|
|
nxt_state <= wait_l4s20;
|
1226 |
|
|
rst_int <= '0';
|
1227 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(79));
|
1228 |
|
|
WHEN wait_l4s20 =>
|
1229 |
|
|
IF counter>=normal_factor THEN
|
1230 |
|
|
nxt_state <= l4s20;
|
1231 |
|
|
ELSE
|
1232 |
|
|
nxt_state <= wait_l4s20;
|
1233 |
|
|
END IF;
|
1234 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(79));
|
1235 |
|
|
rst_int <= '1';
|
1236 |
|
|
WHEN l4s20 =>
|
1237 |
|
|
nxt_state <= wait_new_line4;
|
1238 |
|
|
rst_int <= '0';
|
1239 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(80));
|
1240 |
|
|
WHEN wait_new_line4 =>
|
1241 |
|
|
IF counter>=normal_factor THEN
|
1242 |
|
|
nxt_state <= new_line4;
|
1243 |
|
|
ELSE
|
1244 |
|
|
nxt_state <= wait_new_line4;
|
1245 |
|
|
END IF;
|
1246 |
|
|
lcd_data_int <= '1' & '0' & char2std(lcd_reg(80));
|
1247 |
|
|
rst_int <= '1';
|
1248 |
|
|
WHEN new_line4 =>
|
1249 |
|
|
nxt_state <= wait_renew;
|
1250 |
|
|
rst_int <= '0';
|
1251 |
|
|
lcd_data_int <= "0000000010";
|
1252 |
|
|
WHEN wait_renew =>
|
1253 |
|
|
IF counter>=extended_factor THEN
|
1254 |
|
|
nxt_state <= l1s1;
|
1255 |
|
|
ELSE
|
1256 |
|
|
nxt_state <= wait_renew;
|
1257 |
|
|
END IF;
|
1258 |
|
|
lcd_data_int <= "0000000010";
|
1259 |
|
|
rst_int <= '1';
|
1260 |
|
|
WHEN OTHERS =>
|
1261 |
|
|
nxt_state <= init_start;
|
1262 |
|
|
rst_int <= '0';
|
1263 |
|
|
lcd_data_int <= (OTHERS => '0');
|
1264 |
|
|
END case;
|
1265 |
|
|
END process;
|
1266 |
|
|
END behavioral;
|