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[/] [md5/] [trunk/] [ah_regs.v] - Blame information for rev 6

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/****************************************************************************
Register file
****************************************************************************/
 
 
module ah_regs (
 
               //Inputs 
          rst_n,
               clk,
               DataVld,
               DataIn,
               stateVld,
               stateAIn,
               stateBIn,
               stateCIn,
               stateDIn,
          StateAComb,
          StateBComb,
          StateCComb,
          StateDComb,
          StateEComb,
 
          //Outputs
          StateAReg,
          StateBReg,
          StateCReg,
          StateDReg,
               A_Reg,
               B_Reg,
               C_Reg,
               D_Reg,
               BlockOut
               );
 
`include "ah_params.vh"
 
input                                rst_n;
input                                clk;
input                                DataVld;
input  [DATA_WIDTH - 1:0]            DataIn;
input                                stateVld;
input  [STATE_DWIDTH - 1:0]          stateAIn;
input  [STATE_DWIDTH - 1:0]          stateBIn;
input  [STATE_DWIDTH - 1:0]          stateCIn;
input  [STATE_DWIDTH - 1:0]          stateDIn;
input  [STATE_DWIDTH - 1:0]          StateAComb;
input  [STATE_DWIDTH - 1:0]          StateBComb;
input  [STATE_DWIDTH - 1:0]          StateCComb;
input  [STATE_DWIDTH - 1:0]          StateDComb;
input  [STATE_DWIDTH - 1:0]          StateEComb;
 
 
output  [STATE_DWIDTH - 1:0]          StateAReg;
output  [STATE_DWIDTH - 1:0]          StateBReg;
output  [STATE_DWIDTH - 1:0]          StateCReg;
output  [STATE_DWIDTH - 1:0]          StateDReg;
output  [STATE_DWIDTH - 1:0]          A_Reg;
output  [STATE_DWIDTH - 1:0]          B_Reg;
output  [STATE_DWIDTH - 1:0]          C_Reg;
output  [STATE_DWIDTH - 1:0]          D_Reg;
output  [BLOCK_SIZE-1:0]              BlockOut;
 
reg  [STATE_DWIDTH - 1:0]          StateAReg;
reg  [STATE_DWIDTH - 1:0]          StateBReg;
reg  [STATE_DWIDTH - 1:0]          StateCReg;
reg  [STATE_DWIDTH - 1:0]          StateDReg;
reg  [STATE_DWIDTH - 1:0]          A_Reg;
reg  [STATE_DWIDTH - 1:0]          B_Reg;
reg  [STATE_DWIDTH - 1:0]          C_Reg;
reg  [STATE_DWIDTH - 1:0]          D_Reg;
reg  [DATA_WIDTH - 1:0]            WtData [15:0];
 
assign BlockOut = {WtData[15], WtData[14], WtData[13], WtData[12],
              WtData[11], WtData[10], WtData[9],  WtData[8],
         WtData[7],  WtData[6],  WtData[5],  WtData[4],
         WtData[3],  WtData[2],  WtData[1],  WtData[0]};
 
 
always @(posedge clk)
  begin
   if (DataVld) begin
     WtData[0] <= DataIn;
     WtData[1] <= WtData[0];
     WtData[2] <= WtData[1];
     WtData[3] <= WtData[2];
     WtData[4] <= WtData[3];
     WtData[5] <= WtData[4];
     WtData[6] <= WtData[5];
     WtData[7] <= WtData[6];
     WtData[8] <= WtData[7];
     WtData[9] <= WtData[8];
     WtData[10] <= WtData[9];
     WtData[11] <= WtData[10];
     WtData[12] <= WtData[11];
     WtData[13] <= WtData[12];
     WtData[14] <= WtData[13];
     WtData[15] <= WtData[14];
   end
  end
 
always @(posedge clk or  negedge rst_n)
  begin
    if (!rst_n) begin
      StateAReg <= 32'b0;
      StateBReg <= 32'b0;
      StateCReg <= 32'b0;
      StateDReg <= 32'b0;
    end
    else begin
      if (stateVld) begin
        StateAReg <= stateAIn;
        StateBReg <= stateBIn;
        StateCReg <= stateCIn;
        StateDReg <= stateDIn;
      end
      else begin
        StateAReg <= StateAComb;
        StateBReg <= StateBComb;
        StateCReg <= StateCComb;
        StateDReg <= StateDComb;
      end
    end
  end
 
always @(posedge clk or  negedge rst_n)
  begin
    if (!rst_n) begin
      A_Reg <= 32'b0;
      B_Reg <= 32'b0;
      C_Reg <= 32'b0;
      D_Reg <= 32'b0;
    end
    else begin
      if (stateVld) begin
        A_Reg <= stateAIn;
        B_Reg <= stateBIn;
        C_Reg <= stateCIn;
        D_Reg <= stateDIn;
      end
    end
  end
endmodule

Line No.	Rev	Author	Line
1	2	verilogcor	`/****************************************************************************`
2			`Register file`
3			`****************************************************************************/`
4
5
6			`module ah_regs (`
7
8			`//Inputs`
9			`rst_n,`
10			`clk,`
11			`DataVld,`
12			`DataIn,`
13			`stateVld,`
14			`stateAIn,`
15			`stateBIn,`
16			`stateCIn,`
17			`stateDIn,`
18			`StateAComb,`
19			`StateBComb,`
20			`StateCComb,`
21			`StateDComb,`
22			`StateEComb,`
23
24			`//Outputs`
25			`StateAReg,`
26			`StateBReg,`
27			`StateCReg,`
28			`StateDReg,`
29			`A_Reg,`
30			`B_Reg,`
31			`C_Reg,`
32			`D_Reg,`
33			`BlockOut`
34			`);`
35
36			`include "ah_params.vh"
37
38			`input rst_n;`
39			`input clk;`
40			`input DataVld;`
41			`input [DATA_WIDTH - 1:0] DataIn;`
42			`input stateVld;`
43			`input [STATE_DWIDTH - 1:0] stateAIn;`
44			`input [STATE_DWIDTH - 1:0] stateBIn;`
45			`input [STATE_DWIDTH - 1:0] stateCIn;`
46			`input [STATE_DWIDTH - 1:0] stateDIn;`
47			`input [STATE_DWIDTH - 1:0] StateAComb;`
48			`input [STATE_DWIDTH - 1:0] StateBComb;`
49			`input [STATE_DWIDTH - 1:0] StateCComb;`
50			`input [STATE_DWIDTH - 1:0] StateDComb;`
51			`input [STATE_DWIDTH - 1:0] StateEComb;`
52
53
54			`output [STATE_DWIDTH - 1:0] StateAReg;`
55			`output [STATE_DWIDTH - 1:0] StateBReg;`
56			`output [STATE_DWIDTH - 1:0] StateCReg;`
57			`output [STATE_DWIDTH - 1:0] StateDReg;`
58			`output [STATE_DWIDTH - 1:0] A_Reg;`
59			`output [STATE_DWIDTH - 1:0] B_Reg;`
60			`output [STATE_DWIDTH - 1:0] C_Reg;`
61			`output [STATE_DWIDTH - 1:0] D_Reg;`
62			`output [BLOCK_SIZE-1:0] BlockOut;`
63
64			`reg [STATE_DWIDTH - 1:0] StateAReg;`
65			`reg [STATE_DWIDTH - 1:0] StateBReg;`
66			`reg [STATE_DWIDTH - 1:0] StateCReg;`
67			`reg [STATE_DWIDTH - 1:0] StateDReg;`
68			`reg [STATE_DWIDTH - 1:0] A_Reg;`
69			`reg [STATE_DWIDTH - 1:0] B_Reg;`
70			`reg [STATE_DWIDTH - 1:0] C_Reg;`
71			`reg [STATE_DWIDTH - 1:0] D_Reg;`
72			`reg [DATA_WIDTH - 1:0] WtData [15:0];`
73
74			`assign BlockOut = {WtData[15], WtData[14], WtData[13], WtData[12],`
75			`WtData[11], WtData[10], WtData[9], WtData[8],`
76			`WtData[7], WtData[6], WtData[5], WtData[4],`
77			`WtData[3], WtData[2], WtData[1], WtData[0]};`
78
79
80			`always @(posedge clk)`
81			`begin`
82			`if (DataVld) begin`
83			`WtData[0] <= DataIn;`
84			`WtData[1] <= WtData[0];`
85			`WtData[2] <= WtData[1];`
86			`WtData[3] <= WtData[2];`
87			`WtData[4] <= WtData[3];`
88			`WtData[5] <= WtData[4];`
89			`WtData[6] <= WtData[5];`
90			`WtData[7] <= WtData[6];`
91			`WtData[8] <= WtData[7];`
92			`WtData[9] <= WtData[8];`
93			`WtData[10] <= WtData[9];`
94			`WtData[11] <= WtData[10];`
95			`WtData[12] <= WtData[11];`
96			`WtData[13] <= WtData[12];`
97			`WtData[14] <= WtData[13];`
98			`WtData[15] <= WtData[14];`
99			`end`
100			`end`
101
102			`always @(posedge clk or negedge rst_n)`
103			`begin`
104			`if (!rst_n) begin`
105			`StateAReg <= 32'b0;`
106			`StateBReg <= 32'b0;`
107			`StateCReg <= 32'b0;`
108			`StateDReg <= 32'b0;`
109			`end`
110			`else begin`
111			`if (stateVld) begin`
112			`StateAReg <= stateAIn;`
113			`StateBReg <= stateBIn;`
114			`StateCReg <= stateCIn;`
115			`StateDReg <= stateDIn;`
116			`end`
117			`else begin`
118			`StateAReg <= StateAComb;`
119			`StateBReg <= StateBComb;`
120			`StateCReg <= StateCComb;`
121			`StateDReg <= StateDComb;`
122			`end`
123			`end`
124			`end`
125
126			`always @(posedge clk or negedge rst_n)`
127			`begin`
128			`if (!rst_n) begin`
129			`A_Reg <= 32'b0;`
130			`B_Reg <= 32'b0;`
131			`C_Reg <= 32'b0;`
132			`D_Reg <= 32'b0;`
133			`end`
134			`else begin`
135			`if (stateVld) begin`
136			`A_Reg <= stateAIn;`
137			`B_Reg <= stateBIn;`
138			`C_Reg <= stateCIn;`
139			`D_Reg <= stateDIn;`
140			`end`
141			`end`
142			`end`
143			`endmodule`

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[/] [md5/] [trunk/] [ah_regs.v] - Blame information for rev 6