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[/] [md5/] [trunk/] [hash_misc.v] - Blame information for rev 6

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/********************************************************************************
* Multiplex-demultiplex logic
********************************************************************************/
 
 
module hash_misc (
 
               //Inputs
                 Md5MsgDgstVld,
                 Md5DataVld,
                 Md5DataIn,
 
                 Md5StateAComb,
                 Md5StateBComb,
                 Md5StateCComb,
                 Md5StateDComb,
 
                 Md5Addend0A,
                 Md5Addend0B,
                 Md5Addend1A,
                 Md5Addend1B,
 
                 //Output
 
                 msgDgstVld,
                 MuxedDataVld,
                 MuxedDataIn,
 
                 MuxedStateAComb,
                 MuxedStateBComb,
                 MuxedStateCComb,
                 MuxedStateDComb,
                 MuxedStateEComb,
                 MuxedAddend0A,
                 MuxedAddend0B,
                 MuxedAddend1A,
                 MuxedAddend1B
 
         );
 
`include "ah_params.vh"
`include "md5_params.vh"
 
input                                Md5DataVld;
input [DATA_WIDTH - 1 :0]            Md5DataIn;
input                                Md5MsgDgstVld;
 
input [STATE_DWIDTH - 1:0]           Md5StateAComb;
input [STATE_DWIDTH - 1:0]           Md5StateBComb;
input [STATE_DWIDTH - 1:0]           Md5StateCComb;
input [STATE_DWIDTH - 1:0]           Md5StateDComb;
 
input [STATE_DWIDTH - 1:0]           Md5Addend0A;
input [STATE_DWIDTH - 1:0]           Md5Addend0B;
input [STATE_DWIDTH - 1:0]           Md5Addend1A;
input [STATE_DWIDTH - 1:0]           Md5Addend1B;
 
output                               msgDgstVld;
output [DATA_WIDTH - 1:0]            MuxedDataIn;
output                               MuxedDataVld;
output [STATE_DWIDTH -1:0]           MuxedStateAComb;
output [STATE_DWIDTH -1:0]           MuxedStateBComb;
output [STATE_DWIDTH -1:0]           MuxedStateCComb;
output [STATE_DWIDTH -1:0]           MuxedStateDComb;
output [STATE_DWIDTH -1:0]           MuxedStateEComb;
output [STATE_DWIDTH - 1:0]          MuxedAddend0A;
output [STATE_DWIDTH - 1:0]          MuxedAddend0B;
output [STATE_DWIDTH - 1:0]          MuxedAddend1A;
output [STATE_DWIDTH - 1:0]          MuxedAddend1B;
 
wire                               msgDgstVld;
wire [DATA_WIDTH - 1:0]            MuxedDataIn;
wire                               MuxedDataVld;
wire [STATE_DWIDTH -1:0]           MuxedStateAComb;
wire [STATE_DWIDTH -1:0]           MuxedStateBComb;
wire [STATE_DWIDTH -1:0]           MuxedStateCComb;
wire [STATE_DWIDTH -1:0]           MuxedStateDComb;
wire [STATE_DWIDTH -1:0]           MuxedStateEComb;
wire [STATE_DWIDTH - 1:0]          MuxedAddend0A;
wire [STATE_DWIDTH - 1:0]          MuxedAddend0B;
wire [STATE_DWIDTH - 1:0]          MuxedAddend1A;
wire [STATE_DWIDTH - 1:0]          MuxedAddend1B;
 
assign       msgDgstVld = Md5MsgDgstVld;
assign       MuxedDataIn = Md5DataIn;
assign       MuxedDataVld = Md5DataVld;
 
assign   MuxedStateAComb = Md5StateAComb;
assign   MuxedStateBComb = Md5StateBComb;
assign   MuxedStateCComb = Md5StateCComb;
assign   MuxedStateDComb = Md5StateDComb;
assign   MuxedStateEComb = 32'b0;
 
assign   MuxedAddend0A = Md5Addend0A;
assign   MuxedAddend0B = Md5Addend0B;
assign   MuxedAddend1A = Md5Addend1A;
assign   MuxedAddend1B = Md5Addend1B;
 
endmodule

Line No.	Rev	Author	Line
1	2	verilogcor	`/********************************************************************************`
2			`* Multiplex-demultiplex logic`
3			`********************************************************************************/`
4
5
6			`module hash_misc (`
7
8			`//Inputs`
9			`Md5MsgDgstVld,`
10			`Md5DataVld,`
11			`Md5DataIn,`
12
13			`Md5StateAComb,`
14			`Md5StateBComb,`
15			`Md5StateCComb,`
16			`Md5StateDComb,`
17
18			`Md5Addend0A,`
19			`Md5Addend0B,`
20			`Md5Addend1A,`
21			`Md5Addend1B,`
22
23			`//Output`
24
25			`msgDgstVld,`
26			`MuxedDataVld,`
27			`MuxedDataIn,`
28
29			`MuxedStateAComb,`
30			`MuxedStateBComb,`
31			`MuxedStateCComb,`
32			`MuxedStateDComb,`
33			`MuxedStateEComb,`
34			`MuxedAddend0A,`
35			`MuxedAddend0B,`
36			`MuxedAddend1A,`
37			`MuxedAddend1B`
38
39			`);`
40
41			`include "ah_params.vh"
42			`include "md5_params.vh"
43
44			`input Md5DataVld;`
45			`input [DATA_WIDTH - 1 :0] Md5DataIn;`
46			`input Md5MsgDgstVld;`
47
48			`input [STATE_DWIDTH - 1:0] Md5StateAComb;`
49			`input [STATE_DWIDTH - 1:0] Md5StateBComb;`
50			`input [STATE_DWIDTH - 1:0] Md5StateCComb;`
51			`input [STATE_DWIDTH - 1:0] Md5StateDComb;`
52
53			`input [STATE_DWIDTH - 1:0] Md5Addend0A;`
54			`input [STATE_DWIDTH - 1:0] Md5Addend0B;`
55			`input [STATE_DWIDTH - 1:0] Md5Addend1A;`
56			`input [STATE_DWIDTH - 1:0] Md5Addend1B;`
57
58			`output msgDgstVld;`
59			`output [DATA_WIDTH - 1:0] MuxedDataIn;`
60			`output MuxedDataVld;`
61			`output [STATE_DWIDTH -1:0] MuxedStateAComb;`
62			`output [STATE_DWIDTH -1:0] MuxedStateBComb;`
63			`output [STATE_DWIDTH -1:0] MuxedStateCComb;`
64			`output [STATE_DWIDTH -1:0] MuxedStateDComb;`
65			`output [STATE_DWIDTH -1:0] MuxedStateEComb;`
66			`output [STATE_DWIDTH - 1:0] MuxedAddend0A;`
67			`output [STATE_DWIDTH - 1:0] MuxedAddend0B;`
68			`output [STATE_DWIDTH - 1:0] MuxedAddend1A;`
69			`output [STATE_DWIDTH - 1:0] MuxedAddend1B;`
70
71			`wire msgDgstVld;`
72			`wire [DATA_WIDTH - 1:0] MuxedDataIn;`
73			`wire MuxedDataVld;`
74			`wire [STATE_DWIDTH -1:0] MuxedStateAComb;`
75			`wire [STATE_DWIDTH -1:0] MuxedStateBComb;`
76			`wire [STATE_DWIDTH -1:0] MuxedStateCComb;`
77			`wire [STATE_DWIDTH -1:0] MuxedStateDComb;`
78			`wire [STATE_DWIDTH -1:0] MuxedStateEComb;`
79			`wire [STATE_DWIDTH - 1:0] MuxedAddend0A;`
80			`wire [STATE_DWIDTH - 1:0] MuxedAddend0B;`
81			`wire [STATE_DWIDTH - 1:0] MuxedAddend1A;`
82			`wire [STATE_DWIDTH - 1:0] MuxedAddend1B;`
83
84			`assign msgDgstVld = Md5MsgDgstVld;`
85			`assign MuxedDataIn = Md5DataIn;`
86			`assign MuxedDataVld = Md5DataVld;`
87
88			`assign MuxedStateAComb = Md5StateAComb;`
89			`assign MuxedStateBComb = Md5StateBComb;`
90			`assign MuxedStateCComb = Md5StateCComb;`
91			`assign MuxedStateDComb = Md5StateDComb;`
92			`assign MuxedStateEComb = 32'b0;`
93
94			`assign MuxedAddend0A = Md5Addend0A;`
95			`assign MuxedAddend0B = Md5Addend0B;`
96			`assign MuxedAddend1A = Md5Addend1A;`
97			`assign MuxedAddend1B = Md5Addend1B;`
98
99			`endmodule`

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[/] [md5/] [trunk/] [hash_misc.v] - Blame information for rev 6