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[/] [md5/] [trunk/] [md5_ctrl.v] - Blame information for rev 4

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/********************************************************************************
* Module Name : md5_ctrl
* Description : MD5 computation control logic
*
********************************************************************************/
 
 
module md5_ctrl (
 
                //Inputs
                 clk,
                 rst_n,
                 DataVld,
                 DataIn,
                 ResStateAReg,
                 ResStateBReg,
                 ResStateCReg,
                 ResStateDReg,
 
                //Outputs
                 RoundNum,
                 DataVldExt,
                 Md5Data,
                 MsgDgstVld,
                 MsgDigest
              );
 
 
`include "ah_params.vh"
`include "md5_params.vh"
`include "md5_func.vh"
 
input                                clk;
input                                rst_n;
input                                DataVld;
input  [DATA_WIDTH - 1:0]            DataIn;
input  [STATE_DWIDTH - 1:0]          ResStateAReg;
input  [STATE_DWIDTH - 1:0]          ResStateBReg;
input  [STATE_DWIDTH - 1:0]          ResStateCReg;
input  [STATE_DWIDTH - 1:0]          ResStateDReg;
 
output [5:0]                         RoundNum;
output                               DataVldExt;
output [DATA_WIDTH - 1:0]            Md5Data;
output                               MsgDgstVld;
output [DATA_WIDTH -1:0]             MsgDigest;
 
reg [5:0]                            RoundNum;
reg                                  DataVldTemp;
reg                                  MsgDgstVld_send;
 
wire                                 DataVldExt;
wire [DATA_WIDTH - 1:0]              Md5Data;
wire [MD5_MSG_DIGEST -1:0]           MsgDigest_wire;
reg  [DATA_WIDTH -1:0]               MsgDigest;
wire  [STATE_DWIDTH - 1:0]           ResStateAFlip;
wire  [STATE_DWIDTH - 1:0]           ResStateBFlip;
wire  [STATE_DWIDTH - 1:0]           ResStateCFlip;
wire  [STATE_DWIDTH - 1:0]           ResStateDFlip;
reg   [2:0]                          sending_cnt;
reg   [2:0]                          sending_cnt_r;
reg                                  MsgDgstVld;
wire                                 MsgDgstVld_c;
 
assign ResStateAFlip =  byte_flip(ResStateAReg);
assign ResStateBFlip =  byte_flip(ResStateBReg);
assign ResStateCFlip =  byte_flip(ResStateCReg);
assign ResStateDFlip =  byte_flip(ResStateDReg);
assign MsgDigest_wire = {ResStateAFlip, ResStateBFlip, ResStateCFlip, ResStateDFlip};
 
assign DataVldExt = DataVld | DataVldTemp;
assign Md5Data = DataIn;
 
assign MsgDgstVld_c = (sending_cnt != 0);
 
always @(posedge clk or negedge rst_n)
  begin
    if (!rst_n) begin
      RoundNum <= 0;
      DataVldTemp <= 0;
    end
    else begin
      if (DataVldExt) begin
        RoundNum <= (RoundNum == 63) ? 0 : RoundNum + 1;
        DataVldTemp <= (RoundNum != 63);
      end
      else begin
        RoundNum <= 0;
        DataVldTemp <= 0;
      end
    end
  end
 
always @(posedge clk or negedge rst_n)
  begin
     if (!rst_n) begin
        MsgDgstVld_send <= 1'b0;
        MsgDgstVld <= 1'b0;
     end
     else begin
        MsgDgstVld_send <= (RoundNum == 63);
        MsgDgstVld <= MsgDgstVld_c;
     end
  end
 
always @(posedge clk or negedge rst_n)  begin
   if (!rst_n) begin
       sending_cnt_r <= 3'b0;
   end
   else begin
      sending_cnt_r <= sending_cnt;
   end
end
 
always @(MsgDgstVld_send or sending_cnt_r) begin
   if (MsgDgstVld_send & (sending_cnt_r ==0)) begin
      sending_cnt = 3'b001;
   end
   else if (sending_cnt_r !=0) begin
      sending_cnt = (sending_cnt_r == 3'b100) ? 0 : sending_cnt_r + 1;
   end
   else begin
      sending_cnt = 3'b0;
   end
end
 
always @(posedge clk) begin
   case (sending_cnt)
      3'b001 : begin
         MsgDigest <= MsgDigest_wire[31:0];
      end
      3'b010 : begin
         MsgDigest <= MsgDigest_wire[63:32];
      end
      3'b011 : begin
         MsgDigest <= MsgDigest_wire[95:64];
      end
      3'b100 : begin
         MsgDigest <= MsgDigest_wire[127:96];
      end
      default : begin
         MsgDigest <= 32'b0;
      end
   endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	2	verilogcor	`/********************************************************************************`
2			`* Module Name : md5_ctrl`
3			`* Description : MD5 computation control logic`
4			`*`
5			`********************************************************************************/`
6
7
8			`module md5_ctrl (`
9
10			`//Inputs`
11			`clk,`
12			`rst_n,`
13			`DataVld,`
14			`DataIn,`
15			`ResStateAReg,`
16			`ResStateBReg,`
17			`ResStateCReg,`
18			`ResStateDReg,`
19
20			`//Outputs`
21			`RoundNum,`
22			`DataVldExt,`
23			`Md5Data,`
24			`MsgDgstVld,`
25			`MsgDigest`
26			`);`
27
28
29			`include "ah_params.vh"
30			`include "md5_params.vh"
31			`include "md5_func.vh"
32
33			`input clk;`
34			`input rst_n;`
35			`input DataVld;`
36			`input [DATA_WIDTH - 1:0] DataIn;`
37			`input [STATE_DWIDTH - 1:0] ResStateAReg;`
38			`input [STATE_DWIDTH - 1:0] ResStateBReg;`
39			`input [STATE_DWIDTH - 1:0] ResStateCReg;`
40			`input [STATE_DWIDTH - 1:0] ResStateDReg;`
41
42			`output [5:0] RoundNum;`
43			`output DataVldExt;`
44			`output [DATA_WIDTH - 1:0] Md5Data;`
45			`output MsgDgstVld;`
46			`output [DATA_WIDTH -1:0] MsgDigest;`
47
48			`reg [5:0] RoundNum;`
49			`reg DataVldTemp;`
50			`reg MsgDgstVld_send;`
51
52			`wire DataVldExt;`
53			`wire [DATA_WIDTH - 1:0] Md5Data;`
54			`wire [MD5_MSG_DIGEST -1:0] MsgDigest_wire;`
55			`reg [DATA_WIDTH -1:0] MsgDigest;`
56			`wire [STATE_DWIDTH - 1:0] ResStateAFlip;`
57			`wire [STATE_DWIDTH - 1:0] ResStateBFlip;`
58			`wire [STATE_DWIDTH - 1:0] ResStateCFlip;`
59			`wire [STATE_DWIDTH - 1:0] ResStateDFlip;`
60			`reg [2:0] sending_cnt;`
61			`reg [2:0] sending_cnt_r;`
62			`reg MsgDgstVld;`
63			`wire MsgDgstVld_c;`
64
65			`assign ResStateAFlip = byte_flip(ResStateAReg);`
66			`assign ResStateBFlip = byte_flip(ResStateBReg);`
67			`assign ResStateCFlip = byte_flip(ResStateCReg);`
68			`assign ResStateDFlip = byte_flip(ResStateDReg);`
69			`assign MsgDigest_wire = {ResStateAFlip, ResStateBFlip, ResStateCFlip, ResStateDFlip};`
70
71			`assign DataVldExt = DataVld \| DataVldTemp;`
72			`assign Md5Data = DataIn;`
73
74			`assign MsgDgstVld_c = (sending_cnt != 0);`
75
76			`always @(posedge clk or negedge rst_n)`
77			`begin`
78			`if (!rst_n) begin`
79			`RoundNum <= 0;`
80			`DataVldTemp <= 0;`
81			`end`
82			`else begin`
83			`if (DataVldExt) begin`
84			`RoundNum <= (RoundNum == 63) ? 0 : RoundNum + 1;`
85			`DataVldTemp <= (RoundNum != 63);`
86			`end`
87			`else begin`
88			`RoundNum <= 0;`
89			`DataVldTemp <= 0;`
90			`end`
91			`end`
92			`end`
93
94			`always @(posedge clk or negedge rst_n)`
95			`begin`
96			`if (!rst_n) begin`
97			`MsgDgstVld_send <= 1'b0;`
98			`MsgDgstVld <= 1'b0;`
99			`end`
100			`else begin`
101			`MsgDgstVld_send <= (RoundNum == 63);`
102			`MsgDgstVld <= MsgDgstVld_c;`
103			`end`
104			`end`
105
106			`always @(posedge clk or negedge rst_n) begin`
107			`if (!rst_n) begin`
108			`sending_cnt_r <= 3'b0;`
109			`end`
110			`else begin`
111			`sending_cnt_r <= sending_cnt;`
112			`end`
113			`end`
114
115			`always @(MsgDgstVld_send or sending_cnt_r) begin`
116			`if (MsgDgstVld_send & (sending_cnt_r ==0)) begin`
117			`sending_cnt = 3'b001;`
118			`end`
119			`else if (sending_cnt_r !=0) begin`
120			`sending_cnt = (sending_cnt_r == 3'b100) ? 0 : sending_cnt_r + 1;`
121			`end`
122			`else begin`
123			`sending_cnt = 3'b0;`
124			`end`
125			`end`
126
127			`always @(posedge clk) begin`
128			`case (sending_cnt)`
129			`3'b001 : begin`
130			`MsgDigest <= MsgDigest_wire[31:0];`
131			`end`
132			`3'b010 : begin`
133			`MsgDigest <= MsgDigest_wire[63:32];`
134			`end`
135			`3'b011 : begin`
136			`MsgDigest <= MsgDigest_wire[95:64];`
137			`end`
138			`3'b100 : begin`
139			`MsgDigest <= MsgDigest_wire[127:96];`
140			`end`
141			`default : begin`
142			`MsgDigest <= 32'b0;`
143			`end`
144			`endcase`
145			`end`
146
147			`endmodule`

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[/] [md5/] [trunk/] [md5_ctrl.v] - Blame information for rev 4