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[/] [md5/] [trunk/] [md5_padding.v] - Blame information for rev 4

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/********************************************************************************
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* Module     : md5_padding
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* Description: md5 Padding block
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*
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********************************************************************************
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*          Esencia Technology Proprietary and Confidential
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*          All rights reserved (c) 2005 by Esencia Technolgy
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********************************************************************************/
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module md5_padding (
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         //Inputs
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          clk,
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          rst_n,
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          DataVld,
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          InitVec,
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          DataIn,
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          DataFirst,
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          DataLast,
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          DataNumb,
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          RoundNum,
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         //Outputs 
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          DataBusy,
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          Md5DataIn,
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          Md5DataVld,
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          Md5StateAIn,
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          Md5StateBIn,
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          Md5StateCIn,
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          Md5StateDIn,
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          Md5StateVld
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      );
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`include "md5_params.vh"
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`include "ah_params.vh"
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`include "md5_func.vh"
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input                                clk;
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input                                rst_n;
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input                                DataVld; // Valid flag for Data or InitVec
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input  [DATA_WIDTH - 1:0]            DataIn; // 32 bit DataIn or Initvect
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input                                DataFirst; // First chunk
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input                                DataLast; // Last chunk of data
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input [5:0]                          DataNumb; // Number of valid bits in 
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                                               // last chuck of data
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input [5:0]                          RoundNum;
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input                                InitVec;  // Inidicate Init Vector
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output                                Md5DataVld;
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output  [DATA_WIDTH - 1:0]            Md5DataIn;
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output                                Md5StateVld;
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output  [STATE_DWIDTH - 1:0]          Md5StateAIn;
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output  [STATE_DWIDTH - 1:0]          Md5StateBIn;
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output  [STATE_DWIDTH - 1:0]          Md5StateCIn;
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output  [STATE_DWIDTH - 1:0]          Md5StateDIn;
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output                                DataBusy;
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reg [3:0]                             DinCntReg;
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reg [3:0]                             DinCnt;
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reg [63:0]                            PktLength;
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wire [63:0]                           PktLengthBigEnd;
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reg                                   Md5DataVld;
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reg                                   Md5DataVldTemp;
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reg  [DATA_WIDTH - 1:0]               Md5DataIn;
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reg  [DATA_WIDTH - 1:0]               Md5DataInTemp;
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reg                                   Md5StateVld;
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reg  [STATE_DWIDTH - 1:0]             Md5StateAIn;
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reg  [STATE_DWIDTH - 1:0]             Md5StateBIn;
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reg  [STATE_DWIDTH - 1:0]             Md5StateCIn;
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reg  [STATE_DWIDTH - 1:0]             Md5StateDIn;
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reg [1:0]                             InitVecCnt;
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reg                                   PktEnded;
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wire                                  DataBusy;
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wire [8:0]                            PktLengthMod;
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reg  [2:0]                            SendDataCur;
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reg [2:0]                             SendDataNxt;
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reg                                   Pad1Nxt; // Indicate to pad 1
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                                               // in Next data cycle
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reg                                   Pad1NxtReg;
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reg                                   Send4SecRnd;
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reg                                   Send4SecRndReg;
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assign PktLengthMod = PktLength[8:0]; //PktLength % 512
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assign DataBusy = PktEnded || (RoundNum > 14) || (SendDataCur == 4) ||
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                  (SendDataCur == 5) || (SendDataCur == 6);
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assign PktLengthBigEnd = {PktLength[7:0], PktLength[15:8], PktLength[23:16],
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                         PktLength[31:24], PktLength[39:32], PktLength[47:40],
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                         PktLength[55:48], PktLength[63:56]};
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// Send State Value incase of InitVec
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always @(posedge clk or negedge rst_n) begin
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   if (~rst_n) begin
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     InitVecCnt <= 3'b0;
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     Md5StateVld <= 1'b0;
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   end
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   else begin
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     InitVecCnt <= InitVec  ? (InitVecCnt == 3) ? 0 :
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                   InitVecCnt + 1 : InitVecCnt;
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     Md5StateVld <= (InitVecCnt == 3) && InitVec;
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   end
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end
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always @(posedge clk) begin
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   if (InitVec) begin
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     case (InitVecCnt)
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        3'b000 : begin
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          Md5StateAIn <= DataIn;
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        end
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        3'b001 : begin
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          Md5StateBIn <= DataIn;
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        end
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        3'b010 : begin
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          Md5StateCIn <= DataIn;
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        end
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        3'b011 : begin
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          Md5StateDIn <= DataIn;
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        end
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     endcase
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   end
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end
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// Start Collecting 512 byte (32x16 cycle)
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//
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always @(posedge clk or negedge rst_n) begin
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  if (~rst_n) begin
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     DinCntReg <= 4'b0;
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     PktLength <= 64'b0;
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     PktEnded <= 1'b0;
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     SendDataCur <= 2'b0;
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     Pad1NxtReg <= 1'b0;
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     Send4SecRndReg <= 1'b0;
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  end
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  else begin
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     SendDataCur <= SendDataNxt;
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     Send4SecRndReg <= Send4SecRnd;
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     Pad1NxtReg <= Pad1Nxt;
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     PktEnded <= (DinCntReg == 15) ? 1'b0 : DataLast ?
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                 1'b1 : PktEnded;
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     DinCntReg <= DinCnt;
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     if (DataVld) begin
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        if (DataFirst) begin
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           PktLength <= DataLast ? DataNumb : 32;
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        end
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        else begin
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           PktLength <= DataLast ? PktLength + DataNumb :
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                         PktLength + 32;
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        end
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     end
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  end
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end
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// Data Send FSM to  CORE
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parameter IDLE                 = 0;
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parameter SEND_DATA            = 1;
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parameter SECOND_ROUND_CHK0    = 2;
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parameter SECOND_ROUND_CHK1    = 3;
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parameter WAIT                 = 4;
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parameter WAIT2                = 5;
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parameter SECOND_ROUND         = 6;
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always @(SendDataCur or PktEnded or DinCntReg
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         or DataVld or DataLast or DataNumb or
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         Pad1NxtReg or Send4SecRndReg or RoundNum or
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         DataIn or PktLengthBigEnd ) begin
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    Md5DataVldTemp = 1'b0;
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    Md5DataInTemp = 32'b0;
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    Pad1Nxt = 1'b0;
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    Send4SecRnd = 1'b0;
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    SendDataNxt = 3'b0;
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    DinCnt = 4'b0;
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    case (SendDataCur)
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       IDLE : begin
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          if (DataVld) begin
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             SendDataNxt = SEND_DATA;
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             Md5DataInTemp = DataLast ? PadData(DataNumb, DataIn) : DataIn;
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             Md5DataVldTemp = 1'b1;
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             Pad1Nxt = DataLast && (DataNumb == 32);
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             DinCnt = 0;
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          end
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       end
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       SEND_DATA : begin
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         DinCnt = DinCntReg + 1;
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         Md5DataVldTemp = 1'b1;
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         Pad1Nxt = DataLast && (DataNumb == 32);
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         SendDataNxt =  (DinCntReg < 12) ? SEND_DATA : SECOND_ROUND_CHK0;
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         Md5DataInTemp = Pad1NxtReg ? 32'h80000000 : DataLast ? PadData(DataNumb, DataIn) : PktEnded ?
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                         32'b0 : DataIn;
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       end
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       SECOND_ROUND_CHK0 : begin
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          DinCnt = DinCntReg + 1;
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          Md5DataVldTemp = 1'b1;
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          SendDataNxt = SECOND_ROUND_CHK1;
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          Send4SecRnd = DataLast || Pad1NxtReg;
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          Pad1Nxt = DataLast && (DataNumb == 32);
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          if (DataLast) begin
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             Md5DataInTemp = PadData(DataNumb, DataIn);
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          end
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          else  begin
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             Md5DataInTemp = Pad1NxtReg ? 32'h80000000 :
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                             PktEnded ? PktLengthBigEnd[63:32] : DataIn;
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          end
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       end
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       SECOND_ROUND_CHK1 : begin
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          DinCnt = DinCntReg + 1;
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          Md5DataVldTemp = 1'b1;
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          SendDataNxt = (Send4SecRndReg || DataLast) ? WAIT : IDLE;
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          Pad1Nxt = DataLast && (DataNumb == 32);
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          if (DataLast) begin
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             Md5DataInTemp = PadData(DataNumb, DataIn);
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          end
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          else  begin
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             Md5DataInTemp = Pad1NxtReg ? 32'h80000000 :
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                             PktEnded ? Send4SecRndReg ? 32'b0 :
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                             PktLengthBigEnd[31:0] : DataIn;
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          end
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       end
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       WAIT : begin
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          DinCnt = 0;
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          Md5DataVldTemp = 1'b0;
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          Pad1Nxt = Pad1NxtReg;
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          SendDataNxt = (RoundNum == 63) ? WAIT2 : WAIT;
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       end
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       WAIT2 : begin
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          DinCnt = 0;
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          SendDataNxt =  SECOND_ROUND;
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          Pad1Nxt = Pad1NxtReg;
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          Md5DataVldTemp = 1'b0;
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       end
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       SECOND_ROUND : begin
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          DinCnt = DinCntReg + 1;
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          Pad1Nxt = (DinCntReg == 0) ? Pad1NxtReg : 1'b0;
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          Md5DataVldTemp = (DinCntReg <= 15);
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          SendDataNxt = (DinCntReg == 15) ? IDLE : SECOND_ROUND;
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          if (DinCntReg < 14) begin
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            Md5DataInTemp = Pad1Nxt ? 32'h80000000 : 32'b0;
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          end
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          else begin
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            Md5DataInTemp = (DinCntReg == 14) ? PktLengthBigEnd[63:32] :
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                            PktLengthBigEnd[31:0];
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          end
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       end
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       default : begin
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          Md5DataVldTemp = 1'b0;
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          Md5DataInTemp = 32'b0;
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          Pad1Nxt = 1'b0;
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          Send4SecRnd = 1'b0;
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          DinCnt = 4'b0;
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       end
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    endcase
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end
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// Send Pkt Data 512 byte with padding
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always @(posedge clk or negedge rst_n) begin
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  if (~rst_n) begin
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    Md5DataVld <= 1'b0;
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    Md5DataIn <= 32'b0;
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  end
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  else begin
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     Md5DataVld <= Md5DataVldTemp;
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     Md5DataIn <= Md5DataInTemp;
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  end
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end
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endmodule

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