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mikel262 |
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-- --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2006 --
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-- --
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--------------------------------------------------------------------------------
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--
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-- Title : DCT1D
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-- Design : MDCT Core
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-- Author : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File : DCT1D.VHD
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-- Created : Sat Mar 5 7:37 2006
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--
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--------------------------------------------------------------------------------
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--
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-- Description : 1D Discrete Cosine Transform (1st stage)
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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library WORK;
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use WORK.MDCT_PKG.all;
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--------------------------------------------------------------------------------
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-- ENTITY
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--------------------------------------------------------------------------------
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entity DCT1D is
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port(
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clk : in STD_LOGIC;
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rst : in std_logic;
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dcti : in std_logic_vector(IP_W-1 downto 0);
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idv : in STD_LOGIC;
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romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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reqwrfail : in STD_LOGIC;
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ready : out STD_LOGIC; -- read from FIFO
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odv : out STD_LOGIC;
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dcto : out std_logic_vector(OP_W-1 downto 0);
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romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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ramwe : out STD_LOGIC;
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requestwr : out STD_LOGIC;
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releasewr : out STD_LOGIC
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);
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end DCT1D;
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--------------------------------------------------------------------------------
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-- ARCHITECTURE
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--------------------------------------------------------------------------------
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architecture RTL of DCT1D is
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type STATE_T is
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(
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IDLE,
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GET_ROM,
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SUM,
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WRITE_ODD
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);
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type ISTATE_T is
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(
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IDLE_I,
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ACQUIRE_1ROW,
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WAITF
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);
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type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
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signal ready_reg : STD_LOGIC;
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signal databuf_reg : INPUT_DATA;
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signal latchbuf_reg : INPUT_DATA;
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signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
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signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
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signal inpcnt_reg : UNSIGNED(2 downto 0);
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signal state_reg : STATE_T;
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signal istate_reg : ISTATE_T;
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signal cnt_reg : UNSIGNED(3 downto 0);
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signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal ramwe_s : STD_LOGIC;
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signal latch_done_reg : STD_LOGIC;
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signal requestwr_reg : STD_LOGIC;
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signal releasewr_reg : STD_LOGIC;
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signal completed_reg : STD_LOGIC;
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signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
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begin
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ready_sg:
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ready <= ready_reg;
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ramwe_sg:
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ramwe <= ramwe_s;
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ramdatai_sg:
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ramdatai <= ramdatai_s;
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-- temporary
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odv_sg:
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odv <= ramwe_s;
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dcto_sg:
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dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
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releasewr_sg:
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releasewr <= releasewr_reg;
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requestwr_sg:
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requestwr <= requestwr_reg;
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--------------------------------------
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-- PROCESS
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--------------------------------------
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GET_PROC : process(rst,clk)
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begin
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if rst = '1' then
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inpcnt_reg <= (others => '0');
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ready_reg <= '0';
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latchbuf_reg <= (others => (others => '0'));
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istate_reg <= IDLE_I;
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latch_done_reg <= '0';
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requestwr_reg <= '0';
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elsif clk = '1' and clk'event then
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mikel262 |
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mikel262 |
case istate_reg is
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when IDLE_I =>
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if idv = '1' then
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requestwr_reg <= '1';
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end if;
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if requestwr_reg = '1' then
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requestwr_reg <= '0';
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istate_reg <= ACQUIRE_1ROW;
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end if;
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when ACQUIRE_1ROW =>
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if idv = '1' then
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-- read next data from input FIFO
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ready_reg <= '1';
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if ready_reg = '1' then
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-- right shift input data
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latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
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latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
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inpcnt_reg <= inpcnt_reg + 1;
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if inpcnt_reg = N-1 then
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latch_done_reg <= '1';
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ready_reg <= '0';
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istate_reg <= WAITF;
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end if;
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end if;
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else
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ready_reg <= '0';
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end if;
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-- failure to allocate any memory buffer
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if reqwrfail = '1' then
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-- restart allocation procedure
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istate_reg <= IDLE_I;
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ready_reg <= '0';
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end if;
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when WAITF =>
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-- wait until DCT1D_PROC process 1D DCT computation
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-- before latching new 8 input words
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if state_reg = IDLE then
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latch_done_reg <= '0';
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if completed_reg = '1' then
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istate_reg <= IDLE_I;
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else
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istate_reg <= ACQUIRE_1ROW;
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end if;
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end if;
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when others =>
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istate_reg <= IDLE_I;
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end case;
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end if;
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end process;
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--------------------------------------
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-- PROCESS
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--------------------------------------
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DCT1D_PROC: process(rst, clk)
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begin
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if rst = '1' then
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col_reg <= (others => '0');
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row_reg <= (others => '0');
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state_reg <= IDLE;
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cnt_reg <= (others => '0');
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databuf_reg <= (others => (others => '0'));
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ramwaddro <= (others => '0');
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ramdatai_s <= (others => '0');
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ramwe_s <= '0';
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releasewr_reg <= '0';
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completed_reg <= '0';
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col_tmp_reg <= (others => '0');
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elsif rising_edge(clk) then
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case state_reg is
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----------------------
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-- wait for input data
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----------------------
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when IDLE =>
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releasewr_reg <= '0';
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ramwe_s <= '0';
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-- wait until 8 input words are latched in latchbuf_reg
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-- by GET_PROC
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if latch_done_reg = '1' then
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completed_reg <= '0';
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-- after this sum databuf_reg is in range of -256 to 254 (min to max)
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databuf_reg(0) <= latchbuf_reg(0)+latchbuf_reg(7);
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databuf_reg(1) <= latchbuf_reg(1)+latchbuf_reg(6);
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databuf_reg(2) <= latchbuf_reg(2)+latchbuf_reg(5);
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databuf_reg(3) <= latchbuf_reg(3)+latchbuf_reg(4);
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databuf_reg(4) <= latchbuf_reg(0)-latchbuf_reg(7);
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databuf_reg(5) <= latchbuf_reg(1)-latchbuf_reg(6);
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databuf_reg(6) <= latchbuf_reg(2)-latchbuf_reg(5);
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databuf_reg(7) <= latchbuf_reg(3)-latchbuf_reg(4);
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state_reg <= GET_ROM;
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end if;
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----------------------
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-- get MAC results from ROM even and ROM odd memories
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----------------------
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when GET_ROM =>
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ramwe_s <='0';
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state_reg <= SUM;
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---------------------
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-- do distributed arithmetic sum on even part,
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-- write even part to RAM
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---------------------
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when SUM =>
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ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romedatao0),DA_W) +
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(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
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(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
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(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
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(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
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(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
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(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
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(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
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(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),DA_W)(DA_W-1 downto 12));
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-- write even part
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ramwe_s <= '1';
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-- reverse col/row order for transposition purpose
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ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
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col_reg <= col_reg + 1;
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col_tmp_reg <= col_reg + 2;
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4 |
mikel262 |
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2 |
mikel262 |
state_reg <= WRITE_ODD;
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---------------------
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-- do distributed arithmetic sum on odd part,
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-- write odd part to RAM
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---------------------
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when WRITE_ODD =>
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-- write odd part
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--ramwe_s <= '1';
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ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romodatao0),DA_W) +
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(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
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(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
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(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
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(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
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|
|
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
|
| 318 |
|
|
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
|
| 319 |
|
|
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
|
| 320 |
|
|
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
|
| 321 |
|
|
DA_W)(DA_W-1 downto 12));
|
| 322 |
|
|
|
| 323 |
|
|
-- write odd part
|
| 324 |
|
|
-- reverse col/row order for transposition purpose
|
| 325 |
|
|
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
|
| 326 |
|
|
|
| 327 |
|
|
-- move to next column
|
| 328 |
|
|
col_reg <= col_reg + 1;
|
| 329 |
4 |
mikel262 |
col_tmp_reg <= col_reg + 1;
|
| 330 |
2 |
mikel262 |
|
| 331 |
|
|
-- finished processing one input row
|
| 332 |
|
|
if col_reg = N - 1 then
|
| 333 |
|
|
row_reg <= row_reg + 1;
|
| 334 |
4 |
mikel262 |
col_reg <= (others => '0');
|
| 335 |
|
|
col_tmp_reg <= (others => '0');
|
| 336 |
2 |
mikel262 |
if row_reg = N - 1 then
|
| 337 |
|
|
releasewr_reg <= '1';
|
| 338 |
|
|
completed_reg <= '1';
|
| 339 |
|
|
end if;
|
| 340 |
|
|
state_reg <= IDLE;
|
| 341 |
|
|
else
|
| 342 |
4 |
mikel262 |
|
| 343 |
2 |
mikel262 |
state_reg <= SUM;
|
| 344 |
|
|
|
| 345 |
|
|
end if;
|
| 346 |
|
|
--------------------------------
|
| 347 |
|
|
-- OTHERS
|
| 348 |
|
|
--------------------------------
|
| 349 |
|
|
when others =>
|
| 350 |
|
|
state_reg <= IDLE;
|
| 351 |
|
|
end case;
|
| 352 |
|
|
end if;
|
| 353 |
|
|
end process;
|
| 354 |
|
|
|
| 355 |
4 |
mikel262 |
-- read precomputed MAC results from LUT
|
| 356 |
|
|
romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 357 |
|
|
databuf_reg(0)(0) &
|
| 358 |
|
|
databuf_reg(1)(0) &
|
| 359 |
|
|
databuf_reg(2)(0) &
|
| 360 |
|
|
databuf_reg(3)(0);
|
| 361 |
|
|
romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 362 |
|
|
databuf_reg(0)(1) &
|
| 363 |
|
|
databuf_reg(1)(1) &
|
| 364 |
|
|
databuf_reg(2)(1) &
|
| 365 |
|
|
databuf_reg(3)(1);
|
| 366 |
|
|
romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 367 |
|
|
databuf_reg(0)(2) &
|
| 368 |
|
|
databuf_reg(1)(2) &
|
| 369 |
|
|
databuf_reg(2)(2) &
|
| 370 |
|
|
databuf_reg(3)(2);
|
| 371 |
|
|
romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 372 |
|
|
databuf_reg(0)(3) &
|
| 373 |
|
|
databuf_reg(1)(3) &
|
| 374 |
|
|
databuf_reg(2)(3) &
|
| 375 |
|
|
databuf_reg(3)(3);
|
| 376 |
|
|
romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 377 |
|
|
databuf_reg(0)(4) &
|
| 378 |
|
|
databuf_reg(1)(4) &
|
| 379 |
|
|
databuf_reg(2)(4) &
|
| 380 |
|
|
databuf_reg(3)(4);
|
| 381 |
|
|
romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 382 |
|
|
databuf_reg(0)(5) &
|
| 383 |
|
|
databuf_reg(1)(5) &
|
| 384 |
|
|
databuf_reg(2)(5) &
|
| 385 |
|
|
databuf_reg(3)(5);
|
| 386 |
|
|
romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 387 |
|
|
databuf_reg(0)(6) &
|
| 388 |
|
|
databuf_reg(1)(6) &
|
| 389 |
|
|
databuf_reg(2)(6) &
|
| 390 |
|
|
databuf_reg(3)(6);
|
| 391 |
|
|
romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 392 |
|
|
databuf_reg(0)(7) &
|
| 393 |
|
|
databuf_reg(1)(7) &
|
| 394 |
|
|
databuf_reg(2)(7) &
|
| 395 |
|
|
databuf_reg(3)(7);
|
| 396 |
|
|
romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
| 397 |
|
|
databuf_reg(0)(8) &
|
| 398 |
|
|
databuf_reg(1)(8) &
|
| 399 |
|
|
databuf_reg(2)(8) &
|
| 400 |
|
|
databuf_reg(3)(8);
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
-- odd
|
| 404 |
|
|
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 405 |
|
|
databuf_reg(4)(0) &
|
| 406 |
|
|
databuf_reg(5)(0) &
|
| 407 |
|
|
databuf_reg(6)(0) &
|
| 408 |
|
|
databuf_reg(7)(0);
|
| 409 |
|
|
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 410 |
|
|
databuf_reg(4)(1) &
|
| 411 |
|
|
databuf_reg(5)(1) &
|
| 412 |
|
|
databuf_reg(6)(1) &
|
| 413 |
|
|
databuf_reg(7)(1);
|
| 414 |
|
|
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 415 |
|
|
databuf_reg(4)(2) &
|
| 416 |
|
|
databuf_reg(5)(2) &
|
| 417 |
|
|
databuf_reg(6)(2) &
|
| 418 |
|
|
databuf_reg(7)(2);
|
| 419 |
|
|
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 420 |
|
|
databuf_reg(4)(3) &
|
| 421 |
|
|
databuf_reg(5)(3) &
|
| 422 |
|
|
databuf_reg(6)(3) &
|
| 423 |
|
|
databuf_reg(7)(3);
|
| 424 |
|
|
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 425 |
|
|
databuf_reg(4)(4) &
|
| 426 |
|
|
databuf_reg(5)(4) &
|
| 427 |
|
|
databuf_reg(6)(4) &
|
| 428 |
|
|
databuf_reg(7)(4);
|
| 429 |
|
|
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 430 |
|
|
databuf_reg(4)(5) &
|
| 431 |
|
|
databuf_reg(5)(5) &
|
| 432 |
|
|
databuf_reg(6)(5) &
|
| 433 |
|
|
databuf_reg(7)(5);
|
| 434 |
|
|
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 435 |
|
|
databuf_reg(4)(6) &
|
| 436 |
|
|
databuf_reg(5)(6) &
|
| 437 |
|
|
databuf_reg(6)(6) &
|
| 438 |
|
|
databuf_reg(7)(6);
|
| 439 |
|
|
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 440 |
|
|
databuf_reg(4)(7) &
|
| 441 |
|
|
databuf_reg(5)(7) &
|
| 442 |
|
|
databuf_reg(6)(7) &
|
| 443 |
|
|
databuf_reg(7)(7);
|
| 444 |
|
|
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
| 445 |
|
|
databuf_reg(4)(8) &
|
| 446 |
|
|
databuf_reg(5)(8) &
|
| 447 |
|
|
databuf_reg(6)(8) &
|
| 448 |
|
|
databuf_reg(7)(8);
|
| 449 |
|
|
|
| 450 |
2 |
mikel262 |
end RTL;
|
| 451 |
|
|
--------------------------------------------------------------------------------
|
