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[/] [mdct/] [tags/] [MDCT_REL_B1_2/] [source/] [MDCT.VHD] - Blame information for rev 9

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1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : DCT
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
-- Company     : None
12 
--
13 
--------------------------------------------------------------------------------
14 
--
15 
-- File        : MDCT.VHD
16 
-- Created     : Sat Feb 25 16:12 2006
17 
--
18 
--------------------------------------------------------------------------------
19 
--
20 
--  Description : Discrete Cosine Transform - chip top level (w/ memories)
21 
--
22 
--------------------------------------------------------------------------------
23 
 
24 
 
25 
library IEEE;
26 
  use IEEE.STD_LOGIC_1164.all;
27 
 
28 
library WORK;
29 
  use WORK.MDCT_PKG.all;
30 
 
31 
 
32 
entity MDCT is
33 
        port(
34 
                clk          : in STD_LOGIC;
35 
                rst          : in std_logic;
36 
    dcti         : in std_logic_vector(IP_W-1 downto 0);
37 
    idv          : in STD_LOGIC;
38 
 
39 
    ready        : out STD_LOGIC; -- ready for input data
40 
    odv          : out STD_LOGIC;
41 
    dcto         : out std_logic_vector(COE_W-1 downto 0);
42 
    -- debug
43 
    odv1         : out STD_LOGIC;
44 
    dcto1        : out std_logic_vector(OP_W-1 downto 0)
45 
 
46 
                );
47 
end MDCT;
48 
 
49 
architecture RTL of MDCT is
50 
 
51 
------------------------------
52 
-- 1D DCT
53 
------------------------------
54 
component DCT1D
55 
        port(
56 
                clk          : in STD_LOGIC;
57 
                rst          : in std_logic;
58 
      dcti         : in std_logic_vector(IP_W-1 downto 0);
59 
      idv          : in STD_LOGIC;
60 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
61 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
62 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
63 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
64 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
65 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
66 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
67 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
68 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
69 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
70 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
71 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
72 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
73 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
74 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
75 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
76 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
77 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
78 
      reqwrfail    : in STD_LOGIC;
79 
 
80 
      ready        : out STD_LOGIC; -- read from FIFO
81 
      odv          : out STD_LOGIC;
82 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
83 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
84 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
85 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
86 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
87 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
88 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
89 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
90 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
91 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
92 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
93 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
94 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
95 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
96 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
97 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
98 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
99 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
100 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
101 
      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
102 
      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
103 
      ramwe        : out STD_LOGIC;
104 
      requestwr    : out STD_LOGIC;
105 
      releasewr    : out STD_LOGIC
106 
                );
107 
end component;
108 
 
109 
------------------------------
110 
-- 1D DCT (2nd stage)
111 
------------------------------
112 
component DCT2D
113 
        port(
114 
      clk          : in STD_LOGIC;
115 
      rst          : in std_logic;
116 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
117 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
118 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
119 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
120 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
121 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
122 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
123 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
124 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
125 
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
126 
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
127 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
128 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
129 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
130 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
131 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
132 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
133 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
134 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
135 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
136 
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
137 
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
138 
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
139 
      reqrdfail    : in STD_LOGIC;
140 
      dataready    : in STD_LOGIC;
141 
 
142 
      odv          : out STD_LOGIC;
143 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
144 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
145 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
146 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
147 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
148 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
149 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
150 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
151 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
152 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
153 
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
154 
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
155 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
156 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
157 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
158 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
159 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
160 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
161 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
162 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
163 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
164 
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
165 
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
166 
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
167 
      requestrd    : out STD_LOGIC;
168 
      releaserd    : out STD_LOGIC
169 
);
170 
end component;
171 
 
172 
------------------------------
173 
-- RAM
174 
------------------------------
175 
component RAM
176 
  port (
177 
        d                 : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
178 
        waddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
179 
        raddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
180 
        we                : in  STD_LOGIC;
181 
        clk               : in  STD_LOGIC;
182 
 
183 
        q                 : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
184 
  );
185 
end component;
186 
 
187 
------------------------------
188 
-- ROME
189 
------------------------------
190 
component ROME
191 
  port(
192 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
193 
 
194 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
195 
  );
196 
end component;
197 
 
198 
------------------------------
199 
-- ROMO
200 
------------------------------
201 
component ROMO
202 
  port(
203 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
204 
 
205 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
206 
  );
207 
end component;
208 
 
209 
------------------------------
210 
-- DBUFCTL
211 
------------------------------
212 
component DBUFCTL is
213 
        port(
214 
                clk          : in STD_LOGIC;
215 
                rst          : in STD_LOGIC;
216 
    requestwr    : in STD_LOGIC;
217 
    requestrd    : in STD_LOGIC;
218 
    releasewr    : in STD_LOGIC;
219 
    releaserd    : in STD_LOGIC;
220 
 
221 
    memswitchwr  : out STD_LOGIC;
222 
    memswitchrd  : out STD_LOGIC;
223 
    reqwrfail    : out STD_LOGIC;
224 
    reqrdfail    : out STD_LOGIC;
225 
    dataready    : out STD_LOGIC
226 
);
227 
end component;
228 
 
229 
signal romedatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
230 
signal romedatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
231 
signal romedatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
232 
signal romedatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
233 
signal romedatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
234 
signal romedatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
235 
signal romedatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
236 
signal romedatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
237 
signal romedatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
238 
signal romodatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
239 
signal romodatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
240 
signal romodatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
241 
signal romodatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
242 
signal romodatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
243 
signal romodatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
244 
signal romodatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
245 
signal romodatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
246 
signal romodatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
247 
signal ramdatao_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
248 
signal romeaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
249 
signal romeaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
250 
signal romeaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
251 
signal romeaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
252 
signal romeaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
253 
signal romeaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
254 
signal romeaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
255 
signal romeaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
256 
signal romeaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
257 
signal romoaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
258 
signal romoaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
259 
signal romoaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
260 
signal romoaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
261 
signal romoaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
262 
signal romoaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
263 
signal romoaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
264 
signal romoaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
265 
signal romoaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
266 
signal ramraddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
267 
signal ramwaddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
268 
signal ramdatai_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
269 
signal ramwe_s              : STD_LOGIC;
270 
 
271 
signal rome2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
272 
signal rome2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
273 
signal rome2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
274 
signal rome2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
275 
signal rome2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
276 
signal rome2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
277 
signal rome2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
278 
signal rome2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
279 
signal rome2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
280 
signal rome2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
281 
signal rome2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
282 
signal romo2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
283 
signal romo2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
284 
signal romo2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
285 
signal romo2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
286 
signal romo2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
287 
signal romo2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
288 
signal romo2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
289 
signal romo2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
290 
signal romo2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
291 
signal romo2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
292 
signal romo2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
293 
signal rome2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
294 
signal rome2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
295 
signal rome2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
296 
signal rome2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
297 
signal rome2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
298 
signal rome2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
299 
signal rome2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
300 
signal rome2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
301 
signal rome2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
302 
signal rome2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
303 
signal rome2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
304 
signal romo2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
305 
signal romo2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
306 
signal romo2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
307 
signal romo2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
308 
signal romo2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
309 
signal romo2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
310 
signal romo2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
311 
signal romo2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
312 
signal romo2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
313 
signal romo2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
314 
signal romo2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
315 
signal odv2_s                : STD_LOGIC;
316 
signal dcto2_s               : STD_LOGIC_VECTOR(OP_W-1 downto 0);
317 
signal trigger2_s            : STD_LOGIC;
318 
signal trigger1_s            : STD_LOGIC;
319 
signal ramdatao1_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
320 
signal ramdatao2_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
321 
signal ramwe1_s              : STD_LOGIC;
322 
signal ramwe2_s              : STD_LOGIC;
323 
signal memswitchrd_s         : STD_LOGIC;
324 
signal memswitchwr_s         : STD_LOGIC;
325 
signal reqwrfail_s           : STD_LOGIC;
326 
signal reqrdfail_s           : STD_LOGIC;
327 
signal dataready_s           : STD_LOGIC;
328 
signal requestwr_s           : STD_LOGIC;
329 
signal releasewr_s           : STD_LOGIC;
330 
signal requestrd_s           : STD_LOGIC;
331 
signal releaserd_s           : STD_LOGIC;
332 
 
333 
begin
334 
 
335 
------------------------------
336 
-- 1D DCT port map
337 
------------------------------
338 
U_DCT1D : DCT1D
339 
  port map(
340 
      clk          => clk,
341 
      rst          => rst,
342 
      dcti         => dcti,
343 
      idv          => idv,
344 
      romedatao0   => romedatao0_s,
345 
      romedatao1   => romedatao1_s,
346 
      romedatao2   => romedatao2_s,
347 
      romedatao3   => romedatao3_s,
348 
      romedatao4   => romedatao4_s,
349 
      romedatao5   => romedatao5_s,
350 
      romedatao6   => romedatao6_s,
351 
      romedatao7   => romedatao7_s,
352 
      romedatao8   => romedatao8_s,
353 
      romodatao0   => romodatao0_s,
354 
      romodatao1   => romodatao1_s,
355 
      romodatao2   => romodatao2_s,
356 
      romodatao3   => romodatao3_s,
357 
      romodatao4   => romodatao4_s,
358 
      romodatao5   => romodatao5_s,
359 
      romodatao6   => romodatao6_s,
360 
      romodatao7   => romodatao7_s,
361 
      romodatao8   => romodatao8_s,
362 
      reqwrfail    => reqwrfail_s,
363 
 
364 
      ready        => ready,
365 
      odv          => odv1,
366 
      dcto         => dcto1,
367 
      romeaddro0   => romeaddro0_s,
368 
      romeaddro1   => romeaddro1_s,
369 
      romeaddro2   => romeaddro2_s,
370 
      romeaddro3   => romeaddro3_s,
371 
      romeaddro4   => romeaddro4_s,
372 
      romeaddro5   => romeaddro5_s,
373 
      romeaddro6   => romeaddro6_s,
374 
      romeaddro7   => romeaddro7_s,
375 
      romeaddro8   => romeaddro8_s,
376 
      romoaddro0   => romoaddro0_s,
377 
      romoaddro1   => romoaddro1_s,
378 
      romoaddro2   => romoaddro2_s,
379 
      romoaddro3   => romoaddro3_s,
380 
      romoaddro4   => romoaddro4_s,
381 
      romoaddro5   => romoaddro5_s,
382 
      romoaddro6   => romoaddro6_s,
383 
      romoaddro7   => romoaddro7_s,
384 
      romoaddro8   => romoaddro8_s,
385 
      ramwaddro    => ramwaddro_s,
386 
      ramdatai     => ramdatai_s,
387 
      ramwe        => ramwe_s,
388 
      requestwr    => requestwr_s,
389 
      releasewr    => releasewr_s
390 
                );
391 
 
392 
------------------------------
393 
-- 1D DCT port map
394 
------------------------------
395 
U_DCT2D : DCT2D
396 
  port map(
397 
      clk          => clk,
398 
      rst          => rst,
399 
      romedatao0   => rome2datao0_s,
400 
      romedatao1   => rome2datao1_s,
401 
      romedatao2   => rome2datao2_s,
402 
      romedatao3   => rome2datao3_s,
403 
      romedatao4   => rome2datao4_s,
404 
      romedatao5   => rome2datao5_s,
405 
      romedatao6   => rome2datao6_s,
406 
      romedatao7   => rome2datao7_s,
407 
      romedatao8   => rome2datao8_s,
408 
      romedatao9   => rome2datao9_s,
409 
      romedatao10  => rome2datao10_s,
410 
      romodatao0   => romo2datao0_s,
411 
      romodatao1   => romo2datao1_s,
412 
      romodatao2   => romo2datao2_s,
413 
      romodatao3   => romo2datao3_s,
414 
      romodatao4   => romo2datao4_s,
415 
      romodatao5   => romo2datao5_s,
416 
      romodatao6   => romo2datao6_s,
417 
      romodatao7   => romo2datao7_s,
418 
      romodatao8   => romo2datao8_s,
419 
      romodatao9   => romo2datao9_s,
420 
      romodatao10  => romo2datao10_s,
421 
      ramdatao     => ramdatao_s,
422 
      reqrdfail    => reqrdfail_s,
423 
      dataready    => dataready_s,
424 
 
425 
      odv          => odv,
426 
      dcto         => dcto,
427 
      romeaddro0   => rome2addro0_s,
428 
      romeaddro1   => rome2addro1_s,
429 
      romeaddro2   => rome2addro2_s,
430 
      romeaddro3   => rome2addro3_s,
431 
      romeaddro4   => rome2addro4_s,
432 
      romeaddro5   => rome2addro5_s,
433 
      romeaddro6   => rome2addro6_s,
434 
      romeaddro7   => rome2addro7_s,
435 
      romeaddro8   => rome2addro8_s,
436 
      romeaddro9   => rome2addro9_s,
437 
      romeaddro10  => rome2addro10_s,
438 
      romoaddro0   => romo2addro0_s,
439 
      romoaddro1   => romo2addro1_s,
440 
      romoaddro2   => romo2addro2_s,
441 
      romoaddro3   => romo2addro3_s,
442 
      romoaddro4   => romo2addro4_s,
443 
      romoaddro5   => romo2addro5_s,
444 
      romoaddro6   => romo2addro6_s,
445 
      romoaddro7   => romo2addro7_s,
446 
      romoaddro8   => romo2addro8_s,
447 
      romoaddro9   => romo2addro9_s,
448 
      romoaddro10  => romo2addro10_s,
449 
      ramraddro    => ramraddro_s,
450 
      requestrd    => requestrd_s,
451 
      releaserd    => releaserd_s
452 
                );
453 
 
454 
------------------------------
455 
-- RAM1 port map
456 
------------------------------
457 
U1_RAM : RAM
458 
  port map (
459 
        d          => ramdatai_s,
460 
        waddr      => ramwaddro_s,
461 
        raddr      => ramraddro_s,
462 
        we         => ramwe1_s,
463 
        clk        => clk,
464 
 
465 
        q          => ramdatao1_s
466 
  );
467 
 
468 
------------------------------
469 
-- RAM2 port map
470 
------------------------------
471 
U2_RAM : RAM
472 
  port map (
473 
        d          => ramdatai_s,
474 
        waddr      => ramwaddro_s,
475 
        raddr      => ramraddro_s,
476 
        we         => ramwe2_s,
477 
        clk        => clk,
478 
 
479 
        q          => ramdatao2_s
480 
  );
481 
 
482 
-- double buffer switch
483 
ramwe1_s     <= ramwe_s when memswitchwr_s = '0' else '0';
484 
ramwe2_s     <= ramwe_s when memswitchwr_s = '1' else '0';
485 
ramdatao_s   <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
486 
 
487 
------------------------------
488 
-- DBUFCTL
489 
------------------------------
490 
U_DBUFCTL : DBUFCTL
491 
        port map(
492 
                clk            => clk,
493 
                rst            => rst,
494 
    requestwr      => requestwr_s,
495 
    requestrd      => requestrd_s,
496 
    releasewr      => releasewr_s,
497 
    releaserd      => releaserd_s,
498 
 
499 
    memswitchwr    => memswitchwr_s,
500 
    memswitchrd    => memswitchrd_s,
501 
    reqwrfail      => reqwrfail_s,
502 
    reqrdfail      => reqrdfail_s,
503 
    dataready      => dataready_s
504 
                );
505 
 
506 
------------------------------
507 
-- ROME port map
508 
------------------------------
509 
U1_ROME0 : ROME
510 
  port map(
511 
       addr        => romeaddro0_s,
512 
 
513 
       datao       => romedatao0_s
514 
  );
515 
 
516 
------------------------------
517 
-- ROME port map
518 
------------------------------
519 
U1_ROME1 : ROME
520 
  port map(
521 
       addr        => romeaddro1_s,
522 
 
523 
       datao       => romedatao1_s
524 
  );
525 
 
526 
------------------------------
527 
-- ROME port map
528 
------------------------------
529 
U1_ROME2 : ROME
530 
  port map(
531 
       addr        => romeaddro2_s,
532 
 
533 
       datao       => romedatao2_s
534 
  );
535 
 
536 
------------------------------
537 
-- ROME port map
538 
------------------------------
539 
U1_ROME3 : ROME
540 
  port map(
541 
       addr        => romeaddro3_s,
542 
 
543 
       datao       => romedatao3_s
544 
  );
545 
------------------------------
546 
-- ROME port map
547 
------------------------------
548 
U1_ROME4 : ROME
549 
  port map(
550 
       addr        => romeaddro4_s,
551 
 
552 
       datao       => romedatao4_s
553 
  );
554 
------------------------------
555 
-- ROME port map
556 
------------------------------
557 
U1_ROME5 : ROME
558 
  port map(
559 
       addr        => romeaddro5_s,
560 
 
561 
       datao       => romedatao5_s
562 
  );
563 
------------------------------
564 
-- ROME port map
565 
------------------------------
566 
U1_ROME6 : ROME
567 
  port map(
568 
       addr        => romeaddro6_s,
569 
 
570 
       datao       => romedatao6_s
571 
  );
572 
------------------------------
573 
-- ROME port map
574 
------------------------------
575 
U1_ROME7 : ROME
576 
  port map(
577 
       addr        => romeaddro7_s,
578 
 
579 
       datao       => romedatao7_s
580 
  );
581 
------------------------------
582 
-- ROME port map
583 
------------------------------
584 
U1_ROME8 : ROME
585 
  port map(
586 
       addr        => romeaddro8_s,
587 
 
588 
       datao       => romedatao8_s
589 
  );
590 
 
591 
------------------------------
592 
-- ROMO port map
593 
------------------------------
594 
U1_ROMO0 : ROMO
595 
  port map(
596 
       addr        => romoaddro0_s,
597 
 
598 
       datao       => romodatao0_s
599 
  );
600 
------------------------------
601 
-- ROMO port map
602 
------------------------------
603 
U1_ROMO1 : ROMO
604 
  port map(
605 
       addr        => romoaddro1_s,
606 
 
607 
       datao       => romodatao1_s
608 
  );
609 
------------------------------
610 
-- ROMO port map
611 
------------------------------
612 
U1_ROMO2 : ROMO
613 
  port map(
614 
       addr        => romoaddro2_s,
615 
 
616 
       datao       => romodatao2_s
617 
  );
618 
------------------------------
619 
-- ROMO port map
620 
------------------------------
621 
U1_ROMO3 : ROMO
622 
  port map(
623 
       addr        => romoaddro3_s,
624 
 
625 
       datao       => romodatao3_s
626 
  );
627 
------------------------------
628 
-- ROMO port map
629 
------------------------------
630 
U1_ROMO4 : ROMO
631 
  port map(
632 
       addr        => romoaddro4_s,
633 
 
634 
       datao       => romodatao4_s
635 
  );
636 
------------------------------
637 
-- ROMO port map
638 
------------------------------
639 
U1_ROMO5 : ROMO
640 
  port map(
641 
       addr        => romoaddro5_s,
642 
 
643 
       datao       => romodatao5_s
644 
  );
645 
------------------------------
646 
-- ROMO port map
647 
------------------------------
648 
U1_ROMO6 : ROMO
649 
  port map(
650 
       addr        => romoaddro6_s,
651 
 
652 
       datao       => romodatao6_s
653 
  );
654 
------------------------------
655 
-- ROMO port map
656 
------------------------------
657 
U1_ROMO7 : ROMO
658 
  port map(
659 
       addr        => romoaddro7_s,
660 
 
661 
       datao       => romodatao7_s
662 
  );
663 
------------------------------
664 
-- ROMO port map
665 
------------------------------
666 
U1_ROMO8 : ROMO
667 
  port map(
668 
       addr        => romoaddro8_s,
669 
 
670 
       datao       => romodatao8_s
671 
  );
672 
 
673 
------------------------------
674 
-- 2 stage ROMs
675 
------------------------------
676 
------------------------------
677 
-- ROME port map
678 
------------------------------
679 
U2_ROME0 : ROME
680 
  port map(
681 
       addr        => rome2addro0_s,
682 
 
683 
       datao       => rome2datao0_s
684 
  );
685 
 
686 
------------------------------
687 
-- ROME port map
688 
------------------------------
689 
U2_ROME1 : ROME
690 
  port map(
691 
       addr        => rome2addro1_s,
692 
 
693 
       datao       => rome2datao1_s
694 
  );
695 
 
696 
------------------------------
697 
-- ROME port map
698 
------------------------------
699 
U2_ROME2 : ROME
700 
  port map(
701 
       addr        => rome2addro2_s,
702 
 
703 
       datao       => rome2datao2_s
704 
  );
705 
 
706 
------------------------------
707 
-- ROME port map
708 
------------------------------
709 
U2_ROME3 : ROME
710 
  port map(
711 
       addr        => rome2addro3_s,
712 
 
713 
       datao       => rome2datao3_s
714 
  );
715 
------------------------------
716 
-- ROME port map
717 
------------------------------
718 
U2_ROME4 : ROME
719 
  port map(
720 
       addr        => rome2addro4_s,
721 
 
722 
       datao       => rome2datao4_s
723 
  );
724 
------------------------------
725 
-- ROME port map
726 
------------------------------
727 
U2_ROME5 : ROME
728 
  port map(
729 
       addr        => rome2addro5_s,
730 
 
731 
       datao       => rome2datao5_s
732 
  );
733 
------------------------------
734 
-- ROME port map
735 
------------------------------
736 
U2_ROME6 : ROME
737 
  port map(
738 
       addr        => rome2addro6_s,
739 
 
740 
       datao       => rome2datao6_s
741 
  );
742 
------------------------------
743 
-- ROME port map
744 
------------------------------
745 
U2_ROME7 : ROME
746 
  port map(
747 
       addr        => rome2addro7_s,
748 
 
749 
       datao       => rome2datao7_s
750 
  );
751 
------------------------------
752 
-- ROME port map
753 
------------------------------
754 
U2_ROME8 : ROME
755 
  port map(
756 
       addr        => rome2addro8_s,
757 
 
758 
       datao       => rome2datao8_s
759 
  );
760 
------------------------------
761 
-- ROME port map
762 
------------------------------
763 
U2_ROME9 : ROME
764 
  port map(
765 
       addr        => rome2addro9_s,
766 
 
767 
       datao       => rome2datao9_s
768 
  );
769 
------------------------------
770 
-- ROME port map
771 
------------------------------
772 
U2_ROME10 : ROME
773 
  port map(
774 
       addr        => rome2addro10_s,
775 
 
776 
       datao       => rome2datao10_s
777 
  );
778 
 
779 
------------------------------
780 
-- ROMO port map
781 
------------------------------
782 
U2_ROMO0 : ROMO
783 
  port map(
784 
       addr        => romo2addro0_s,
785 
 
786 
       datao       => romo2datao0_s
787 
  );
788 
------------------------------
789 
-- ROMO port map
790 
------------------------------
791 
U2_ROMO1 : ROMO
792 
  port map(
793 
       addr        => romo2addro1_s,
794 
 
795 
       datao       => romo2datao1_s
796 
  );
797 
------------------------------
798 
-- ROMO port map
799 
------------------------------
800 
U2_ROMO2 : ROMO
801 
  port map(
802 
       addr        => romo2addro2_s,
803 
 
804 
       datao       => romo2datao2_s
805 
  );
806 
------------------------------
807 
-- ROMO port map
808 
------------------------------
809 
U2_ROMO3 : ROMO
810 
  port map(
811 
       addr        => romo2addro3_s,
812 
 
813 
       datao       => romo2datao3_s
814 
  );
815 
------------------------------
816 
-- ROMO port map
817 
------------------------------
818 
U2_ROMO4 : ROMO
819 
  port map(
820 
       addr        => romo2addro4_s,
821 
 
822 
       datao       => romo2datao4_s
823 
  );
824 
------------------------------
825 
-- ROMO port map
826 
------------------------------
827 
U2_ROMO5 : ROMO
828 
  port map(
829 
       addr        => romo2addro5_s,
830 
 
831 
       datao       => romo2datao5_s
832 
  );
833 
------------------------------
834 
-- ROMO port map
835 
------------------------------
836 
U2_ROMO6 : ROMO
837 
  port map(
838 
       addr        => romo2addro6_s,
839 
 
840 
       datao       => romo2datao6_s
841 
  );
842 
------------------------------
843 
-- ROMO port map
844 
------------------------------
845 
U2_ROMO7 : ROMO
846 
  port map(
847 
       addr        => romo2addro7_s,
848 
 
849 
       datao       => romo2datao7_s
850 
  );
851 
------------------------------
852 
-- ROMO port map
853 
------------------------------
854 
U2_ROMO8 : ROMO
855 
  port map(
856 
       addr        => romo2addro8_s,
857 
 
858 
       datao       => romo2datao8_s
859 
  );
860 
------------------------------
861 
-- ROMO port map
862 
------------------------------
863 
U2_ROMO9 : ROMO
864 
  port map(
865 
       addr        => romo2addro9_s,
866 
 
867 
       datao       => romo2datao9_s
868 
  );
869 
------------------------------
870 
-- ROMO port map
871 
------------------------------
872 
U2_ROMO10 : ROMO
873 
  port map(
874 
       addr        => romo2addro10_s,
875 
 
876 
       datao       => romo2datao10_s
877 
  );
878 
 
879 
end RTL;

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