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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2006                                --
--                                                                            --
--------------------------------------------------------------------------------
--
-- Title       : DCT1D
-- Design      : MDCT Core
-- Author      : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File        : DCT1D.VHD
-- Created     : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
--  Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.NUMERIC_STD.all;
 
library WORK;
  use WORK.MDCT_PKG.all;
 
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
        port(
                  clk          : in STD_LOGIC;
                  rst          : in std_logic;
      dcti         : in std_logic_vector(IP_W-1 downto 0);
      idv          : in STD_LOGIC;
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      reqwrfail    : in STD_LOGIC;
 
      ready        : out STD_LOGIC; -- read from FIFO
      odv          : out STD_LOGIC;
      dcto         : out std_logic_vector(OP_W-1 downto 0);
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      ramwe        : out STD_LOGIC;
      requestwr    : out STD_LOGIC;
      releasewr    : out STD_LOGIC
                );
end DCT1D;
 
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
 
  type STATE_T is
  (
    MEMREQ,
    IDLE,
    GET_ROM,
    SUM,
    WRITE_ODD
  );
 
  type ISTATE_T is
  (
    ACQUIRE_1ROW
  );
 
  type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
 
  signal ready_reg      : STD_LOGIC;
  signal databuf_reg    : INPUT_DATA;
  signal latchbuf_reg   : INPUT_DATA;
  signal col_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal row_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal inpcnt_reg     : UNSIGNED(2 downto 0);
  signal state_reg      : STATE_T;
  signal istate_reg     : ISTATE_T;
  signal cnt_reg        : UNSIGNED(3 downto 0);
  signal ramdatai_s     : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
  signal ramwe_s        : STD_LOGIC;
  signal latch_done_reg : STD_LOGIC;
  signal requestwr_reg  : STD_LOGIC;
  signal releasewr_reg  : STD_LOGIC;
  signal col_tmp_reg    : UNSIGNED(RAMADRR_W/2-1 downto 0);
begin
 
  ready_sg:
  ready    <= ready_reg;
 
  ramwe_sg:
  ramwe    <= ramwe_s;
 
  ramdatai_sg:
  ramdatai <= ramdatai_s;
 
  -- temporary
  odv_sg:
  odv      <= ramwe_s;
  dcto_sg:
  dcto     <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
 
  releasewr_sg:
  releasewr <= releasewr_reg;
  requestwr_sg:
  requestwr <= requestwr_reg;
 
  --------------------------------------
  -- PROCESS
  --------------------------------------
  GET_PROC : process(rst,clk)
  begin
    if rst = '1' then
      inpcnt_reg     <= (others => '0');
      ready_reg      <= '0';
      latchbuf_reg   <= (others => (others => '0'));
      latch_done_reg <= '0';
    elsif clk = '1' and clk'event then
 
      if latch_done_reg = '0' or
         (state_reg = IDLE and reqwrfail = '0') then
 
        -- wait until DCT1D_PROC process 1D DCT computation 
        -- before latching new 8 input words
        if state_reg = IDLE and reqwrfail = '0' then
          latch_done_reg <= '0';
        end if;
 
        if idv = '1' then
          -- read next data from input FIFO
          ready_reg  <= '1';
 
          if ready_reg = '1' then
            -- right shift input data
            latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
            latchbuf_reg(N-1)          <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
            inpcnt_reg   <= inpcnt_reg + 1;
 
            if inpcnt_reg = N-1 then
              latch_done_reg <= '1';
              ready_reg  <= '0';
            end if;
          end if;
        else
          ready_reg  <= '0';
        end if;
      end if;
    end if;
  end process;
 
  --------------------------------------
  -- PROCESS
  --------------------------------------
  DCT1D_PROC: process(rst, clk)
  begin
    if rst = '1' then
      col_reg       <= (others => '0');
      row_reg       <= (others => '0');
      state_reg     <= MEMREQ;
      cnt_reg       <= (others => '0');
      databuf_reg   <= (others => (others => '0'));
      ramwaddro     <= (others => '0');
      ramdatai_s    <= (others => '0');
      ramwe_s       <= '0';
      releasewr_reg <= '0';
      col_tmp_reg   <= (others => '0');
      requestwr_reg <= '0';
    elsif rising_edge(clk) then
 
      case state_reg is
 
        when MEMREQ =>
 
          ramwe_s       <= '0';
 
          -- release memory fully written
          releasewr_reg <= '0';
 
          -- request free memory for writing
          requestwr_reg <= '1';
 
          -- DBUFCTL 1T delay
          if requestwr_reg = '1' then
            requestwr_reg <= '0';
            state_reg <= IDLE;
          end if;
 
        ----------------------
        -- wait for input data
        ----------------------
        when IDLE =>
 
          ramwe_s       <= '0';
 
          -- failure to allocate any memory buffer
          if reqwrfail = '1' then
             -- restart allocation procedure
             state_reg  <= MEMREQ;
          -- wait until 8 input words are latched in latchbuf_reg
          -- by GET_PROC                    
          elsif latch_done_reg = '1' then
            -- after this sum databuf_reg is in range of -256 to 254 (min to max) 
            databuf_reg(0)  <= latchbuf_reg(0)+latchbuf_reg(7);
            databuf_reg(1)  <= latchbuf_reg(1)+latchbuf_reg(6);
            databuf_reg(2)  <= latchbuf_reg(2)+latchbuf_reg(5);
            databuf_reg(3)  <= latchbuf_reg(3)+latchbuf_reg(4);
            databuf_reg(4)  <= latchbuf_reg(0)-latchbuf_reg(7);
            databuf_reg(5)  <= latchbuf_reg(1)-latchbuf_reg(6);
            databuf_reg(6)  <= latchbuf_reg(2)-latchbuf_reg(5);
            databuf_reg(7)  <= latchbuf_reg(3)-latchbuf_reg(4);
            state_reg       <= GET_ROM;
          end if;
 
        ----------------------
        -- get MAC results from ROM even and ROM odd memories
        ----------------------
        when GET_ROM =>
 
           ramwe_s   <='0';
 
           state_reg <= SUM;
 
        ---------------------
        -- do distributed arithmetic sum on even part,
        -- write even part to RAM
        ---------------------  
        when SUM =>
 
          ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
            (RESIZE(SIGNED(romedatao0),DA_W) +
            (RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
            (RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
            (RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
            (RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
            (RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
            (RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
            (RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
            (RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),DA_W)(DA_W-1 downto 12));
 
          -- write even part
          ramwe_s   <= '1';
          -- reverse col/row order for transposition purpose
          ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
 
          col_reg <= col_reg + 1;
          col_tmp_reg <= col_reg + 2;
 
 
          state_reg <= WRITE_ODD;
 
        ---------------------
        -- do distributed arithmetic sum on odd part,
        -- write odd part to RAM
        ---------------------
        when WRITE_ODD =>
 
          -- write odd part
          --ramwe_s   <= '1';
 
          ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
            (RESIZE(SIGNED(romodatao0),DA_W) +
            (RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
            (RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
            (RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
            (RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
            (RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
            (RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
            (RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
            (RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
            DA_W)(DA_W-1 downto 12));
 
          -- write odd part
          -- reverse col/row order for transposition purpose
          ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
 
          -- move to next column
          col_reg <= col_reg + 1;
          col_tmp_reg <= col_reg + 1;
 
          -- finished processing one input row
          if col_reg = N - 1 then
            row_reg         <= row_reg + 1;
            col_reg         <= (others => '0');
            col_tmp_reg     <= (others => '0');
            if row_reg = N - 1 then
              releasewr_reg <= '1';
              state_reg     <= MEMREQ;
            else
              state_reg     <= IDLE;
            end if;
          else
            state_reg       <= SUM;
          end if;
        --------------------------------
        -- OTHERS
        --------------------------------
        when others =>
          state_reg  <= IDLE;
      end case;
    end if;
  end process;
 
  -- read precomputed MAC results from LUT
  romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(0) &
           databuf_reg(1)(0) &
           databuf_reg(2)(0) &
           databuf_reg(3)(0);
  romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(1) &
           databuf_reg(1)(1) &
           databuf_reg(2)(1) &
           databuf_reg(3)(1);
  romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(2) &
           databuf_reg(1)(2) &
           databuf_reg(2)(2) &
           databuf_reg(3)(2);
  romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(3) &
           databuf_reg(1)(3) &
           databuf_reg(2)(3) &
           databuf_reg(3)(3);
  romeaddro4  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(4) &
           databuf_reg(1)(4) &
           databuf_reg(2)(4) &
           databuf_reg(3)(4);
  romeaddro5  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(5) &
           databuf_reg(1)(5) &
           databuf_reg(2)(5) &
           databuf_reg(3)(5);
  romeaddro6  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(6) &
           databuf_reg(1)(6) &
           databuf_reg(2)(6) &
           databuf_reg(3)(6);
  romeaddro7  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(7) &
           databuf_reg(1)(7) &
           databuf_reg(2)(7) &
           databuf_reg(3)(7);
  romeaddro8  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(8) &
           databuf_reg(1)(8) &
           databuf_reg(2)(8) &
           databuf_reg(3)(8);
 
 
  -- odd
  romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(0) &
             databuf_reg(5)(0) &
             databuf_reg(6)(0) &
             databuf_reg(7)(0);
  romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(1) &
             databuf_reg(5)(1) &
             databuf_reg(6)(1) &
             databuf_reg(7)(1);
  romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(2) &
             databuf_reg(5)(2) &
             databuf_reg(6)(2) &
             databuf_reg(7)(2);
  romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(3) &
             databuf_reg(5)(3) &
             databuf_reg(6)(3) &
             databuf_reg(7)(3);
  romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(4) &
             databuf_reg(5)(4) &
             databuf_reg(6)(4) &
             databuf_reg(7)(4);
  romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(5) &
             databuf_reg(5)(5) &
             databuf_reg(6)(5) &
             databuf_reg(7)(5);
  romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(6) &
             databuf_reg(5)(6) &
             databuf_reg(6)(6) &
             databuf_reg(7)(6);
  romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(7) &
             databuf_reg(5)(7) &
             databuf_reg(6)(7) &
             databuf_reg(7)(7);
  romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(8) &
             databuf_reg(5)(8) &
             databuf_reg(6)(8) &
             databuf_reg(7)(8);
 
end RTL;
--------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	2	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2006 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`--`
8			`-- Title : DCT1D`
9			`-- Design : MDCT Core`
10			`-- Author : Michal Krepa`
11			`--`
12			`--------------------------------------------------------------------------------`
13			`--`
14			`-- File : DCT1D.VHD`
15			`-- Created : Sat Mar 5 7:37 2006`
16			`--`
17			`--------------------------------------------------------------------------------`
18			`--`
19			`-- Description : 1D Discrete Cosine Transform (1st stage)`
20			`--`
21			`--------------------------------------------------------------------------------`
22
23
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.all;`
26			`use IEEE.NUMERIC_STD.all;`
27
28			`library WORK;`
29			`use WORK.MDCT_PKG.all;`
30
31			`--------------------------------------------------------------------------------`
32			`-- ENTITY`
33			`--------------------------------------------------------------------------------`
34			`entity DCT1D is`
35			`port(`
36			`clk : in STD_LOGIC;`
37			`rst : in std_logic;`
38			`dcti : in std_logic_vector(IP_W-1 downto 0);`
39			`idv : in STD_LOGIC;`
40			`romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
41			`romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
42			`romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
43			`romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
44			`romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
45			`romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
46			`romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
47			`romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
48			`romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
49			`romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
50			`romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
51			`romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
52			`romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
53			`romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
54			`romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
55			`romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
56			`romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
57			`romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
58			`reqwrfail : in STD_LOGIC;`
59
60			`ready : out STD_LOGIC; -- read from FIFO`
61			`odv : out STD_LOGIC;`
62			`dcto : out std_logic_vector(OP_W-1 downto 0);`
63			`romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
64			`romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
65			`romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
66			`romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
67			`romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
68			`romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
69			`romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
70			`romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
71			`romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
72			`romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
73			`romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
74			`romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
75			`romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
76			`romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
77			`romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
78			`romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
79			`romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
80			`romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
81			`ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);`
82			`ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
83			`ramwe : out STD_LOGIC;`
84			`requestwr : out STD_LOGIC;`
85			`releasewr : out STD_LOGIC`
86			`);`
87			`end DCT1D;`
88
89			`--------------------------------------------------------------------------------`
90			`-- ARCHITECTURE`
91			`--------------------------------------------------------------------------------`
92			`architecture RTL of DCT1D is`
93
94			`type STATE_T is`
95			`(`
96	10	mikel262	`MEMREQ,`
97	2	mikel262	`IDLE,`
98			`GET_ROM,`
99			`SUM,`
100			`WRITE_ODD`
101			`);`
102
103			`type ISTATE_T is`
104			`(`
105	7	mikel262	`ACQUIRE_1ROW`
106	2	mikel262	`);`
107
108			`type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);`
109
110			`signal ready_reg : STD_LOGIC;`
111			`signal databuf_reg : INPUT_DATA;`
112			`signal latchbuf_reg : INPUT_DATA;`
113			`signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
114			`signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
115			`signal inpcnt_reg : UNSIGNED(2 downto 0);`
116			`signal state_reg : STATE_T;`
117			`signal istate_reg : ISTATE_T;`
118			`signal cnt_reg : UNSIGNED(3 downto 0);`
119			`signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
120			`signal ramwe_s : STD_LOGIC;`
121			`signal latch_done_reg : STD_LOGIC;`
122			`signal requestwr_reg : STD_LOGIC;`
123			`signal releasewr_reg : STD_LOGIC;`
124			`signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
125			`begin`
126
127			`ready_sg:`
128			`ready <= ready_reg;`
129
130			`ramwe_sg:`
131			`ramwe <= ramwe_s;`
132
133			`ramdatai_sg:`
134			`ramdatai <= ramdatai_s;`
135
136			`-- temporary`
137			`odv_sg:`
138			`odv <= ramwe_s;`
139			`dcto_sg:`
140			`dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;`
141
142			`releasewr_sg:`
143			`releasewr <= releasewr_reg;`
144			`requestwr_sg:`
145			`requestwr <= requestwr_reg;`
146
147			`--------------------------------------`
148			`-- PROCESS`
149			`--------------------------------------`
150			`GET_PROC : process(rst,clk)`
151			`begin`
152			`if rst = '1' then`
153			`inpcnt_reg <= (others => '0');`
154			`ready_reg <= '0';`
155			`latchbuf_reg <= (others => (others => '0'));`
156			`latch_done_reg <= '0';`
157			`elsif clk = '1' and clk'event then`
158	4	mikel262
159	10	mikel262	`if latch_done_reg = '0' or`
160			`(state_reg = IDLE and reqwrfail = '0') then`
161
162			`-- wait until DCT1D_PROC process 1D DCT computation`
163			`-- before latching new 8 input words`
164			`if state_reg = IDLE and reqwrfail = '0' then`
165			`latch_done_reg <= '0';`
166			`end if;`
167	2	mikel262
168	10	mikel262	`if idv = '1' then`
169			`-- read next data from input FIFO`
170			`ready_reg <= '1';`
171	2	mikel262
172	10	mikel262	`if ready_reg = '1' then`
173			`-- right shift input data`
174			`latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);`
175			`latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;`
176
177			`inpcnt_reg <= inpcnt_reg + 1;`
178
179			`if inpcnt_reg = N-1 then`
180			`latch_done_reg <= '1';`
181	7	mikel262	`ready_reg <= '0';`
182	10	mikel262	`end if;`
183	7	mikel262	`end if;`
184	10	mikel262	`else`
185			`ready_reg <= '0';`
186			`end if;`
187			`end if;`
188	2	mikel262	`end if;`
189			`end process;`
190
191			`--------------------------------------`
192			`-- PROCESS`
193			`--------------------------------------`
194			`DCT1D_PROC: process(rst, clk)`
195			`begin`
196			`if rst = '1' then`
197			`col_reg <= (others => '0');`
198			`row_reg <= (others => '0');`
199	10	mikel262	`state_reg <= MEMREQ;`
200	2	mikel262	`cnt_reg <= (others => '0');`
201			`databuf_reg <= (others => (others => '0'));`
202			`ramwaddro <= (others => '0');`
203			`ramdatai_s <= (others => '0');`
204			`ramwe_s <= '0';`
205			`releasewr_reg <= '0';`
206			`col_tmp_reg <= (others => '0');`
207	10	mikel262	`requestwr_reg <= '0';`
208	2	mikel262	`elsif rising_edge(clk) then`
209
210			`case state_reg is`
211
212	10	mikel262	`when MEMREQ =>`
213
214			`ramwe_s <= '0';`
215
216			`-- release memory fully written`
217			`releasewr_reg <= '0';`
218
219			`-- request free memory for writing`
220			`requestwr_reg <= '1';`
221
222			`-- DBUFCTL 1T delay`
223			`if requestwr_reg = '1' then`
224			`requestwr_reg <= '0';`
225			`state_reg <= IDLE;`
226			`end if;`
227
228	2	mikel262	`----------------------`
229			`-- wait for input data`
230			`----------------------`
231			`when IDLE =>`
232	10	mikel262
233	2	mikel262	`ramwe_s <= '0';`
234	10	mikel262
235			`-- failure to allocate any memory buffer`
236			`if reqwrfail = '1' then`
237			`-- restart allocation procedure`
238			`state_reg <= MEMREQ;`
239	2	mikel262	`-- wait until 8 input words are latched in latchbuf_reg`
240			`-- by GET_PROC`
241	10	mikel262	`elsif latch_done_reg = '1' then`
242	2	mikel262	`-- after this sum databuf_reg is in range of -256 to 254 (min to max)`
243			`databuf_reg(0) <= latchbuf_reg(0)+latchbuf_reg(7);`
244			`databuf_reg(1) <= latchbuf_reg(1)+latchbuf_reg(6);`
245			`databuf_reg(2) <= latchbuf_reg(2)+latchbuf_reg(5);`
246			`databuf_reg(3) <= latchbuf_reg(3)+latchbuf_reg(4);`
247			`databuf_reg(4) <= latchbuf_reg(0)-latchbuf_reg(7);`
248			`databuf_reg(5) <= latchbuf_reg(1)-latchbuf_reg(6);`
249			`databuf_reg(6) <= latchbuf_reg(2)-latchbuf_reg(5);`
250			`databuf_reg(7) <= latchbuf_reg(3)-latchbuf_reg(4);`
251	10	mikel262	`state_reg <= GET_ROM;`
252			`end if;`
253	2	mikel262
254			`----------------------`
255			`-- get MAC results from ROM even and ROM odd memories`
256			`----------------------`
257			`when GET_ROM =>`
258
259	10	mikel262	`ramwe_s <='0';`
260
261	2	mikel262	`state_reg <= SUM;`
262
263			`---------------------`
264			`-- do distributed arithmetic sum on even part,`
265			`-- write even part to RAM`
266			`---------------------`
267			`when SUM =>`
268
269			`ramdatai_s <= STD_LOGIC_VECTOR(RESIZE`
270			`(RESIZE(SIGNED(romedatao0),DA_W) +`
271			`(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +`
272			`(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +`
273			`(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +`
274			`(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +`
275			`(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +`
276			`(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +`
277			`(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -`
278			`(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),DA_W)(DA_W-1 downto 12));`
279
280			`-- write even part`
281			`ramwe_s <= '1';`
282			`-- reverse col/row order for transposition purpose`
283			`ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);`
284
285			`col_reg <= col_reg + 1;`
286			`col_tmp_reg <= col_reg + 2;`
287
288	4	mikel262
289	2	mikel262	`state_reg <= WRITE_ODD;`
290
291			`---------------------`
292			`-- do distributed arithmetic sum on odd part,`
293			`-- write odd part to RAM`
294			`---------------------`
295			`when WRITE_ODD =>`
296
297			`-- write odd part`
298			`--ramwe_s <= '1';`
299
300			`ramdatai_s <= STD_LOGIC_VECTOR(RESIZE`
301			`(RESIZE(SIGNED(romodatao0),DA_W) +`
302			`(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +`
303			`(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +`
304			`(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +`
305			`(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +`
306			`(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +`
307			`(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +`
308			`(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -`
309			`(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),`
310			`DA_W)(DA_W-1 downto 12));`
311
312			`-- write odd part`
313			`-- reverse col/row order for transposition purpose`
314			`ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);`
315
316			`-- move to next column`
317			`col_reg <= col_reg + 1;`
318	4	mikel262	`col_tmp_reg <= col_reg + 1;`
319	2	mikel262
320			`-- finished processing one input row`
321			`if col_reg = N - 1 then`
322			`row_reg <= row_reg + 1;`
323	4	mikel262	`col_reg <= (others => '0');`
324			`col_tmp_reg <= (others => '0');`
325	2	mikel262	`if row_reg = N - 1 then`
326			`releasewr_reg <= '1';`
327	10	mikel262	`state_reg <= MEMREQ;`
328			`else`
329			`state_reg <= IDLE;`
330	2	mikel262	`end if;`
331	10	mikel262	`else`
332			`state_reg <= SUM;`
333	2	mikel262	`end if;`
334			`--------------------------------`
335			`-- OTHERS`
336			`--------------------------------`
337			`when others =>`
338			`state_reg <= IDLE;`
339			`end case;`
340			`end if;`
341			`end process;`
342
343	4	mikel262	`-- read precomputed MAC results from LUT`
344			`romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
345			`databuf_reg(0)(0) &`
346			`databuf_reg(1)(0) &`
347			`databuf_reg(2)(0) &`
348			`databuf_reg(3)(0);`
349			`romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
350			`databuf_reg(0)(1) &`
351			`databuf_reg(1)(1) &`
352			`databuf_reg(2)(1) &`
353			`databuf_reg(3)(1);`
354			`romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
355			`databuf_reg(0)(2) &`
356			`databuf_reg(1)(2) &`
357			`databuf_reg(2)(2) &`
358			`databuf_reg(3)(2);`
359			`romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
360			`databuf_reg(0)(3) &`
361			`databuf_reg(1)(3) &`
362			`databuf_reg(2)(3) &`
363			`databuf_reg(3)(3);`
364			`romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
365			`databuf_reg(0)(4) &`
366			`databuf_reg(1)(4) &`
367			`databuf_reg(2)(4) &`
368			`databuf_reg(3)(4);`
369			`romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
370			`databuf_reg(0)(5) &`
371			`databuf_reg(1)(5) &`
372			`databuf_reg(2)(5) &`
373			`databuf_reg(3)(5);`
374			`romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
375			`databuf_reg(0)(6) &`
376			`databuf_reg(1)(6) &`
377			`databuf_reg(2)(6) &`
378			`databuf_reg(3)(6);`
379			`romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
380			`databuf_reg(0)(7) &`
381			`databuf_reg(1)(7) &`
382			`databuf_reg(2)(7) &`
383			`databuf_reg(3)(7);`
384			`romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &`
385			`databuf_reg(0)(8) &`
386			`databuf_reg(1)(8) &`
387			`databuf_reg(2)(8) &`
388			`databuf_reg(3)(8);`
389
390
391			`-- odd`
392			`romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
393			`databuf_reg(4)(0) &`
394			`databuf_reg(5)(0) &`
395			`databuf_reg(6)(0) &`
396			`databuf_reg(7)(0);`
397			`romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
398			`databuf_reg(4)(1) &`
399			`databuf_reg(5)(1) &`
400			`databuf_reg(6)(1) &`
401			`databuf_reg(7)(1);`
402			`romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
403			`databuf_reg(4)(2) &`
404			`databuf_reg(5)(2) &`
405			`databuf_reg(6)(2) &`
406			`databuf_reg(7)(2);`
407			`romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
408			`databuf_reg(4)(3) &`
409			`databuf_reg(5)(3) &`
410			`databuf_reg(6)(3) &`
411			`databuf_reg(7)(3);`
412			`romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
413			`databuf_reg(4)(4) &`
414			`databuf_reg(5)(4) &`
415			`databuf_reg(6)(4) &`
416			`databuf_reg(7)(4);`
417			`romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
418			`databuf_reg(4)(5) &`
419			`databuf_reg(5)(5) &`
420			`databuf_reg(6)(5) &`
421			`databuf_reg(7)(5);`
422			`romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
423			`databuf_reg(4)(6) &`
424			`databuf_reg(5)(6) &`
425			`databuf_reg(6)(6) &`
426			`databuf_reg(7)(6);`
427			`romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
428			`databuf_reg(4)(7) &`
429			`databuf_reg(5)(7) &`
430			`databuf_reg(6)(7) &`
431			`databuf_reg(7)(7);`
432			`romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
433			`databuf_reg(4)(8) &`
434			`databuf_reg(5)(8) &`
435			`databuf_reg(6)(8) &`
436			`databuf_reg(7)(8);`
437
438	2	mikel262	`end RTL;`
439			`--------------------------------------------------------------------------------`

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