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[/] [mdct/] [tags/] [MDCT_REL_B1_3/] [source/] [ROMO.VHD] - Blame information for rev 24

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--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--
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-- Title       : DCT
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-- Design      : MDCT Core
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-- Author      : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File        : ROMO.VHD
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-- Created     : Sat Mar 5 7:37 2006
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--
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--------------------------------------------------------------------------------
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--
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--  Description : ROM for DCT matrix constant cosine coefficients (odd part)
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--
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--------------------------------------------------------------------------------
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-- 5:0
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-- 5:4 = select matrix row (1 out of 4)
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-- 3:0 = select precomputed MAC ( 1 out of 16)
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library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use ieee.numeric_std.all;
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  use WORK.MDCT_PKG.all;
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entity ROMO is
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  port(
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       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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       clk          : in  STD_LOGIC;
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       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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  );
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end ROMO;
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architecture RTL of ROMO is
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  type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
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            of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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  constant rom : ROM_TYPE :=
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    (
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       (others => '0'),
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       std_logic_vector( GP ),
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       std_logic_vector( FP ),
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       std_logic_vector( FP+GP ),
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       std_logic_vector( EP ),
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       std_logic_vector( EP+GP ),
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       std_logic_vector( EP+FP ),
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       std_logic_vector( EP+FP+GP ),
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       std_logic_vector( DP ),
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       std_logic_vector( DP+GP ),
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       std_logic_vector( DP+FP ),
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       std_logic_vector( DP+FP+GP ),
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       std_logic_vector( DP+EP ),
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       std_logic_vector( DP+EP+GP ),
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       std_logic_vector( DP+EP+FP ),
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       std_logic_vector( DP+EP+FP+GP ),
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       (others => '0'),
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       std_logic_vector( FM ),
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       std_logic_vector( DM ),
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       std_logic_vector( DM+FM ),
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       std_logic_vector( GM ),
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       std_logic_vector( GM+FM ),
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       std_logic_vector( GM+DM ),
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       std_logic_vector( GM+DM+FM ),
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       std_logic_vector( EP ),
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       std_logic_vector( EP+FM ),
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       std_logic_vector( EP+DM ),
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       std_logic_vector( EP+DM+FM ),
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       std_logic_vector( EP+GM ),
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       std_logic_vector( EP+GM+FM ),
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       std_logic_vector( EP+GM+DM ),
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       std_logic_vector( EP+GM+DM+FM ),
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       (others => '0'),
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       std_logic_vector( EP ),
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       std_logic_vector( GP ),
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       std_logic_vector( EP+GP ),
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       std_logic_vector( DM ),
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       std_logic_vector( DM+EP ),
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       std_logic_vector( DM+GP ),
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       std_logic_vector( DM+GP+EP ),
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       std_logic_vector( FP ),
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       std_logic_vector( FP+EP ),
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       std_logic_vector( FP+GP ),
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       std_logic_vector( FP+GP+EP ),
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       std_logic_vector( FP+DM ),
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       std_logic_vector( FP+DM+EP ),
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       std_logic_vector( FP+DM+GP ),
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       std_logic_vector( FP+DM+GP+EP ),
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       (others => '0'),
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       std_logic_vector( DM ),
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       std_logic_vector( EP ),
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       std_logic_vector( EP+DM ),
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       std_logic_vector( FM ),
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       std_logic_vector( FM+DM ),
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       std_logic_vector( FM+EP ),
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       std_logic_vector( FM+EP+DM ),
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       std_logic_vector( GP ),
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       std_logic_vector( GP+DM ),
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       std_logic_vector( GP+EP ),
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       std_logic_vector( GP+EP+DM ),
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       std_logic_vector( GP+FM ),
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       std_logic_vector( GP+FM+DM ),
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       std_logic_vector( GP+FM+EP ),
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       std_logic_vector( GP+FM+EP+DM )
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       );
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  signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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  datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
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  process(clk)
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  begin
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   if clk = '1' and clk'event then
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     addr_reg <= addr;
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   end if;
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  end process;
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end RTL;
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