URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] [mdct/] [tags/] [MDCT_REL_B1_3/] [source/] [xilinx/] [ROMO.VHD] - Blame information for rev 12

Line No.	Rev	Author	Line
1	11	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2006 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`--`
8			`-- Title : DCT`
9			`-- Design : MDCT Core`
10			`-- Author : Michal Krepa`
11			`--`
12			`--------------------------------------------------------------------------------`
13			`--`
14			`-- File : ROMO.VHD`
15			`-- Created : Sat Mar 5 7:37 2006`
16			`--`
17			`--------------------------------------------------------------------------------`
18			`--`
19			`-- Description : ROM for DCT matrix constant cosine coefficients (odd part)`
20			`--`
21			`--------------------------------------------------------------------------------`
22
23			`-- 5:0`
24			`-- 5:4 = select matrix row (1 out of 4)`
25			`-- 3:0 = select precomputed MAC ( 1 out of 16)`
26
27			`library IEEE;`
28			`use IEEE.STD_LOGIC_1164.all;`
29			`use ieee.numeric_std.all;`
30			`use WORK.MDCT_PKG.all;`
31
32			`entity ROMO is`
33			`port(`
34			`addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
35			`clk : in STD_LOGIC;`
36
37			`datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)`
38			`);`
39
40			`end ROMO;`
41
42			`architecture XILINX of ROMO is`
43
44			`component romo_xil`
45			`port`
46			`(`
47			`A: IN std_logic_VECTOR(5 downto 0);`
48			`CLK: IN std_logic;`
49			`QSPO: OUT std_logic_VECTOR(13 downto 0)`
50			`);`
51			`end component;`
52
53			`begin`
54
55			`U1 : romo_xil`
56			`port map`
57			`(`
58			`A => addr,`
59			`CLK => clk,`
60			`QSPO => datao`
61			`);`
62
63			`end XILINX;`
64