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mikel262 |
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-- This file is owned and controlled by Xilinx and must be used --
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-- solely for design, simulation, implementation and creation of --
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-- design files limited to Xilinx devices or technologies. Use --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- and immediately terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support --
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-- appliances, devices, or systems. Use in such applications are --
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-- expressly prohibited. --
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-- --
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-- (c) Copyright 1995-2004 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file rome_xil.vhd when simulating
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-- the core, rome_xil. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Guide".
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-- The synopsys directives "translate_off/translate_on" specified
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-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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-- synopsys translate_off
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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Library XilinxCoreLib;
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ENTITY rome_xil IS
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port (
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A: IN std_logic_VECTOR(5 downto 0);
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CLK: IN std_logic;
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QSPO: OUT std_logic_VECTOR(13 downto 0));
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END rome_xil;
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ARCHITECTURE rome_xil_a OF rome_xil IS
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component wrapped_rome_xil
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port (
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A: IN std_logic_VECTOR(5 downto 0);
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CLK: IN std_logic;
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QSPO: OUT std_logic_VECTOR(13 downto 0));
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end component;
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-- Configuration specification
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for all : wrapped_rome_xil use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
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generic map(
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c_qualify_we => 0,
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c_mem_type => 0,
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c_has_qdpo_rst => 0,
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c_has_qspo => 1,
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c_has_qspo_rst => 0,
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c_has_dpo => 0,
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c_has_qdpo_clk => 0,
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c_has_d => 0,
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c_qce_joined => 0,
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c_width => 14,
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c_reg_a_d_inputs => 0,
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c_latency => 1,
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c_has_we => 0,
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c_has_spo => 0,
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c_depth => 64,
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c_has_i_ce => 0,
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c_default_data => "0",
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c_default_data_radix => 2,
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c_has_dpra => 0,
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c_has_clk => 1,
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c_enable_rlocs => 1,
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c_generate_mif => 1,
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c_addr_width => 6,
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c_has_qspo_ce => 0,
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c_has_qdpo_srst => 0,
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c_mux_type => 0,
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c_has_spra => 0,
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c_has_qdpo => 0,
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c_mem_init_file => "c:/elektronika/dct/mdct/source/xilinx/rome_xil.mif",
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c_reg_dpra_input => 0,
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c_has_rd_en => 0,
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c_has_qspo_srst => 0,
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c_read_mif => 1,
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c_sync_enable => 0,
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c_has_qdpo_ce => 0);
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BEGIN
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U0 : wrapped_rome_xil
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port map (
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A => A,
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CLK => CLK,
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QSPO => QSPO);
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END rome_xil_a;
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-- synopsys translate_on
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