OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] [mdct/] [tags/] [MDCT_REL_B1_5/] [source/] [DCT2D.VHD] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : DCT2D
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
--
12 
--------------------------------------------------------------------------------
13 
--
14 
-- File        : DCT2D.VHD
15 
-- Created     : Sat Mar 28 22:32 2006
16 
--
17 
--------------------------------------------------------------------------------
18 
--
19 
--  Description : 1D Discrete Cosine Transform (second stage)
20 
--
21 
--------------------------------------------------------------------------------
22 
 
23 
 
24 
library IEEE;
25 
  use IEEE.STD_LOGIC_1164.all;
26 
  use ieee.numeric_std.all;
27 
 
28 
library WORK;
29 
  use WORK.MDCT_PKG.all;
30 
 
31 
entity DCT2D is
32 
        port(
33 
      clk          : in STD_LOGIC;
34 
      rst          : in std_logic;
35 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
36 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
37 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
38 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
39 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
40 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
41 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
42 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
43 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
44 
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
45 
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
46 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
47 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
48 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
49 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
50 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
51 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
52 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
53 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
54 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
55 
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
56 
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
57 
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
58 
      reqrdfail    : in STD_LOGIC;
59 
      dataready    : in STD_LOGIC;
60 
 
61 
      odv          : out STD_LOGIC;
62 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
63 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
64 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
65 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
66 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
67 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
68 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
69 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
70 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
71 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
72 
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
73 
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
74 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
75 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
76 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
77 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
78 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
79 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
80 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
81 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
82 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
83 
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
84 
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
85 
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
86 
      requestrd    : out STD_LOGIC;
87 
      releaserd    : out STD_LOGIC
88 
 
89 
                );
90 
end DCT2D;
91 
 
92 
architecture RTL of DCT2D is
93 
 
94 
  type STATE2_T is
95 
  (
96 
    IDLE,
97 
    GET_ROM,
98 
    SUM,
99 
    WRITE_ODD
100 
  );
101 
 
102 
  type ISTATE2_T is
103 
  (
104 
    IDLE_I,
105 
    WAIT_RAM,
106 
    ACQUIRE_1ROW,
107 
    WAITF
108 
  );
109 
 
110 
  type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
111 
 
112 
  signal databuf_reg    : input_data2;
113 
  signal latchbuf_reg   : input_data2;
114 
  signal col_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
115 
  signal row_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
116 
  signal state_reg      : STATE2_T;
117 
  signal istate_reg     : ISTATE2_T;
118 
  signal cnt_reg        : UNSIGNED(3 downto 0);
119 
  signal latch_done_reg : STD_LOGIC;
120 
  signal rowram_reg     : UNSIGNED(RAMADRR_W/2-1 downto 0);
121 
  signal colram_reg     : UNSIGNED(RAMADRR_W/2 downto 0);
122 
  signal requestrd_reg  : STD_LOGIC;
123 
  signal releaserd_reg  : STD_LOGIC;
124 
  signal completed_reg  : STD_LOGIC;
125 
  signal col_tmp_reg    : UNSIGNED(RAMADRR_W/2-1 downto 0);
126 
 
127 
begin
128 
 
129 
  ramraddro_sg:
130 
  ramraddro  <= STD_LOGIC_VECTOR(rowram_reg & colram_reg(2 downto 0));
131 
 
132 
  requestrd_sg:
133 
  requestrd  <= requestrd_reg;
134 
 
135 
  releaserd_sg:
136 
  releaserd  <= releaserd_reg;
137 
 
138 
  GET_PROC : process(rst,clk)
139 
  begin
140 
    if rst = '1' then
141 
      rowram_reg     <= (others => '0');
142 
      colram_reg     <= (others => '0');
143 
      latchbuf_reg   <= (others => (others => '0'));
144 
      istate_reg     <= IDLE_I;
145 
      latch_done_reg <= '0';
146 
      completed_reg  <= '0';
147 
      requestrd_reg  <= '0';
148 
      releaserd_reg  <= '0';
149 
    elsif clk = '1' and clk'event then
150 
      case istate_reg is
151 
 
152 
        ----------------------
153 
        -- IDLE
154 
        ----------------------
155 
        when IDLE_I =>
156 
          -- one of ram buffers has new data
157 
          if dataready = '1' then
158 
            requestrd_reg <= '1';
159 
          end if;
160 
          -- give 1T delay needed by DBUFCTL
161 
          if requestrd_reg = '1' then
162 
            requestrd_reg <= '0';
163 
            istate_reg <= ACQUIRE_1ROW;
164 
          end if;
165 
 
166 
        ----------------------
167 
        -- latch input data to barrel shifter
168 
        ----------------------
169 
        when ACQUIRE_1ROW =>
170 
 
171 
          -- not starting from zero b/c of RAM 1T delay
172 
          if colram_reg /= 0 then
173 
            -- right shift input data
174 
            latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
175 
            latchbuf_reg(N-1)          <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
176 
          end if;
177 
 
178 
          colram_reg  <= colram_reg + 1;
179 
 
180 
          -- not N-1
181 
          if colram_reg = N then
182 
            -- finished reading 64 point 1D DCT from RAM
183 
            if rowram_reg = N-1 then
184 
              -- release memory
185 
              releaserd_reg <= '1';
186 
              completed_reg <= '1';
187 
            end if;
188 
            colram_reg  <= (others => '0');
189 
            rowram_reg  <= rowram_reg + 1;
190 
            -- 8 point input latched
191 
            latch_done_reg <= '1';
192 
            istate_reg  <= WAITF;
193 
          end if;
194 
 
195 
          -- failure to allocate memory buffer
196 
          -- should never happen?
197 
          if reqrdfail = '1' then
198 
            istate_reg <= IDLE_I;
199 
          end if;
200 
 
201 
        ----------------------
202 
        -- wait until latched input is processed by DCT
203 
        ----------------------
204 
        when WAITF =>
205 
          releaserd_reg <= '0';
206 
          -- wait until DCT1D_PROC process 1D DCT computation
207 
          -- before latching new 8 input words
208 
          if state_reg = IDLE then
209 
            latch_done_reg  <= '0';
210 
            if completed_reg = '1' then
211 
              completed_reg <= '0';
212 
              istate_reg    <= IDLE_I;
213 
            else
214 
              istate_reg <= ACQUIRE_1ROW;
215 
            end if;
216 
          end if;
217 
 
218 
        when others =>
219 
          istate_reg <= IDLE_I;
220 
      end case;
221 
    end if;
222 
  end process;
223 
 
224 
 
225 
  DCT1D_PROC: process(rst, clk)
226 
  begin
227 
    if rst = '1' then
228 
      col_reg      <= (others => '0');
229 
      row_reg      <= (others => '0');
230 
      state_reg    <= IDLE;
231 
      cnt_reg      <= (others => '0');
232 
      databuf_reg  <= (others => (others => '0'));
233 
      romeaddro0    <= (others => '0');
234 
      romeaddro1    <= (others => '0');
235 
      romeaddro2    <= (others => '0');
236 
      romeaddro3    <= (others => '0');
237 
      romeaddro4    <= (others => '0');
238 
      romeaddro5    <= (others => '0');
239 
      romeaddro6    <= (others => '0');
240 
      romeaddro7    <= (others => '0');
241 
      romeaddro8    <= (others => '0');
242 
      romeaddro9    <= (others => '0');
243 
      romeaddro10   <= (others => '0');
244 
      romoaddro0    <= (others => '0');
245 
      romoaddro1    <= (others => '0');
246 
      romoaddro2    <= (others => '0');
247 
      romoaddro3    <= (others => '0');
248 
      romoaddro4    <= (others => '0');
249 
      romoaddro5    <= (others => '0');
250 
      romoaddro6    <= (others => '0');
251 
      romoaddro7    <= (others => '0');
252 
      romoaddro8    <= (others => '0');
253 
      romoaddro9    <= (others => '0');
254 
      romoaddro10   <= (others => '0');
255 
      odv           <= '0';
256 
      dcto          <= (others => '0');
257 
      col_tmp_reg   <= (others => '0');
258 
    elsif rising_edge(clk) then
259 
 
260 
      case state_reg is
261 
 
262 
        ----------------------
263 
        -- wait for input data
264 
        ----------------------
265 
        when IDLE =>
266 
 
267 
          odv <= '0';
268 
          -- wait until 8 input words are latched in latchbuf_reg
269 
          -- by GET_PROC
270 
          if latch_done_reg = '1' then
271 
            -- after this sum databuf_reg is in range of -256 to 254 (min to max)
272 
            databuf_reg(0)  <= latchbuf_reg(0)+latchbuf_reg(7);
273 
            databuf_reg(1)  <= latchbuf_reg(1)+latchbuf_reg(6);
274 
            databuf_reg(2)  <= latchbuf_reg(2)+latchbuf_reg(5);
275 
            databuf_reg(3)  <= latchbuf_reg(3)+latchbuf_reg(4);
276 
            databuf_reg(4)  <= latchbuf_reg(0)-latchbuf_reg(7);
277 
            databuf_reg(5)  <= latchbuf_reg(1)-latchbuf_reg(6);
278 
            databuf_reg(6)  <= latchbuf_reg(2)-latchbuf_reg(5);
279 
            databuf_reg(7)  <= latchbuf_reg(3)-latchbuf_reg(4);
280 
            state_reg   <= GET_ROM;
281 
          end if;
282 
 
283 
        ----------------------
284 
        -- get MAC results from ROM even and ROM odd memories
285 
        ----------------------
286 
        when GET_ROM =>
287 
 
288 
           odv <= '0';
289 
 
290 
           -- read precomputed MAC results from LUT
291 
           romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
292 
                     databuf_reg(0)(0) &
293 
                     databuf_reg(1)(0) &
294 
                     databuf_reg(2)(0) &
295 
                     databuf_reg(3)(0);
296 
           romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
297 
                     databuf_reg(0)(1) &
298 
                     databuf_reg(1)(1) &
299 
                     databuf_reg(2)(1) &
300 
                     databuf_reg(3)(1);
301 
           romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
302 
                     databuf_reg(0)(2) &
303 
                     databuf_reg(1)(2) &
304 
                     databuf_reg(2)(2) &
305 
                     databuf_reg(3)(2);
306 
           romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
307 
                     databuf_reg(0)(3) &
308 
                     databuf_reg(1)(3) &
309 
                     databuf_reg(2)(3) &
310 
                     databuf_reg(3)(3);
311 
           romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
312 
                     databuf_reg(0)(4) &
313 
                     databuf_reg(1)(4) &
314 
                     databuf_reg(2)(4) &
315 
                     databuf_reg(3)(4);
316 
           romeaddro5  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
317 
                     databuf_reg(0)(5) &
318 
                     databuf_reg(1)(5) &
319 
                     databuf_reg(2)(5) &
320 
                     databuf_reg(3)(5);
321 
           romeaddro6  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
322 
                     databuf_reg(0)(6) &
323 
                     databuf_reg(1)(6) &
324 
                     databuf_reg(2)(6) &
325 
                     databuf_reg(3)(6);
326 
           romeaddro7  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
327 
                     databuf_reg(0)(7) &
328 
                     databuf_reg(1)(7) &
329 
                     databuf_reg(2)(7) &
330 
                     databuf_reg(3)(7);
331 
           romeaddro8  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
332 
                     databuf_reg(0)(8) &
333 
                     databuf_reg(1)(8) &
334 
                     databuf_reg(2)(8) &
335 
                     databuf_reg(3)(8);
336 
           romeaddro9  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
337 
                     databuf_reg(0)(9) &
338 
                     databuf_reg(1)(9) &
339 
                     databuf_reg(2)(9) &
340 
                     databuf_reg(3)(9);
341 
           romeaddro10  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
342 
                     databuf_reg(0)(10) &
343 
                     databuf_reg(1)(10) &
344 
                     databuf_reg(2)(10) &
345 
                     databuf_reg(3)(10);
346 
 
347 
           state_reg <= SUM;
348 
 
349 
        ---------------------
350 
        -- do distributed arithmetic sum on even part,
351 
        -- write even part to RAM
352 
        ---------------------
353 
        when SUM =>
354 
 
355 
          -- (a0 +
356 
          -- a1*2 +
357 
          -- (a2 + a3*2)*4 +
358 
          -- a4 * 2^4 +
359 
          -- a5*2 * 2^4 +
360 
          -- (a6 +
361 
          -- a7*2)*2^6 )/
362 
          -- 2^11
363 
          dcto <= STD_LOGIC_VECTOR(RESIZE
364 
            (RESIZE(SIGNED(romedatao0),DA2_W) +
365 
            (RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
366 
            (RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +
367 
            (RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
368 
            (RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
369 
            (RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
370 
            (RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +
371 
            (RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
372 
            (RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
373 
            (RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
374 
            (RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
375 
            DA2_W)(DA2_W-1 downto 12));
376 
 
377 
          -- write even part
378 
          odv   <= '1';
379 
 
380 
          col_reg <= col_reg + 1;
381 
          col_tmp_reg <= col_reg + 2;
382 
 
383 
           romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
384 
                     databuf_reg(4)(0) &
385 
                     databuf_reg(5)(0) &
386 
                     databuf_reg(6)(0) &
387 
                     databuf_reg(7)(0);
388 
           romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
389 
                     databuf_reg(4)(1) &
390 
                     databuf_reg(5)(1) &
391 
                     databuf_reg(6)(1) &
392 
                     databuf_reg(7)(1);
393 
           romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
394 
                     databuf_reg(4)(2) &
395 
                     databuf_reg(5)(2) &
396 
                     databuf_reg(6)(2) &
397 
                     databuf_reg(7)(2);
398 
           romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
399 
                     databuf_reg(4)(3) &
400 
                     databuf_reg(5)(3) &
401 
                     databuf_reg(6)(3) &
402 
                     databuf_reg(7)(3);
403 
           romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
404 
                     databuf_reg(4)(4) &
405 
                     databuf_reg(5)(4) &
406 
                     databuf_reg(6)(4) &
407 
                     databuf_reg(7)(4);
408 
           romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
409 
                     databuf_reg(4)(5) &
410 
                     databuf_reg(5)(5) &
411 
                     databuf_reg(6)(5) &
412 
                     databuf_reg(7)(5);
413 
           romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
414 
                     databuf_reg(4)(6) &
415 
                     databuf_reg(5)(6) &
416 
                     databuf_reg(6)(6) &
417 
                     databuf_reg(7)(6);
418 
           romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
419 
                     databuf_reg(4)(7) &
420 
                     databuf_reg(5)(7) &
421 
                     databuf_reg(6)(7) &
422 
                     databuf_reg(7)(7);
423 
           romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
424 
                     databuf_reg(4)(8) &
425 
                     databuf_reg(5)(8) &
426 
                     databuf_reg(6)(8) &
427 
                     databuf_reg(7)(8);
428 
           romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
429 
                     databuf_reg(4)(9) &
430 
                     databuf_reg(5)(9) &
431 
                     databuf_reg(6)(9) &
432 
                     databuf_reg(7)(9);
433 
           romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
434 
                     databuf_reg(4)(10) &
435 
                     databuf_reg(5)(10) &
436 
                     databuf_reg(6)(10) &
437 
                     databuf_reg(7)(10);
438 
 
439 
          state_reg <= WRITE_ODD;
440 
 
441 
        ---------------------
442 
        -- do distributed arithmetic sum on odd part,
443 
        -- write odd part to RAM
444 
        ---------------------
445 
        when WRITE_ODD =>
446 
 
447 
          dcto <= STD_LOGIC_VECTOR(RESIZE
448 
            (RESIZE(SIGNED(romodatao0),DA2_W) +
449 
            (RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
450 
            (RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +
451 
            (RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
452 
            (RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
453 
            (RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
454 
            (RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +
455 
            (RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
456 
            (RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
457 
            (RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
458 
            (RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
459 
            DA2_W)(DA2_W-1 downto 12));
460 
 
461 
          col_reg <= col_reg + 1;
462 
 
463 
          -- finished processing one input row (1 x N)
464 
          if col_reg = N - 1 then
465 
            row_reg <= row_reg + 1;
466 
            col_reg <= (others => '0');
467 
            state_reg  <= IDLE;
468 
          else
469 
 
470 
            -- read precomputed MAC results from LUT
471 
            romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
472 
                     databuf_reg(0)(0) &
473 
                     databuf_reg(1)(0) &
474 
                     databuf_reg(2)(0) &
475 
                     databuf_reg(3)(0);
476 
            romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
477 
                     databuf_reg(0)(1) &
478 
                     databuf_reg(1)(1) &
479 
                     databuf_reg(2)(1) &
480 
                     databuf_reg(3)(1);
481 
            romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
482 
                     databuf_reg(0)(2) &
483 
                     databuf_reg(1)(2) &
484 
                     databuf_reg(2)(2) &
485 
                     databuf_reg(3)(2);
486 
            romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
487 
                     databuf_reg(0)(3) &
488 
                     databuf_reg(1)(3) &
489 
                     databuf_reg(2)(3) &
490 
                     databuf_reg(3)(3);
491 
            romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
492 
                     databuf_reg(0)(4) &
493 
                     databuf_reg(1)(4) &
494 
                     databuf_reg(2)(4) &
495 
                     databuf_reg(3)(4);
496 
            romeaddro5  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
497 
                     databuf_reg(0)(5) &
498 
                     databuf_reg(1)(5) &
499 
                     databuf_reg(2)(5) &
500 
                     databuf_reg(3)(5);
501 
            romeaddro6  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
502 
                     databuf_reg(0)(6) &
503 
                     databuf_reg(1)(6) &
504 
                     databuf_reg(2)(6) &
505 
                     databuf_reg(3)(6);
506 
            romeaddro7  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
507 
                     databuf_reg(0)(7) &
508 
                     databuf_reg(1)(7) &
509 
                     databuf_reg(2)(7) &
510 
                     databuf_reg(3)(7);
511 
            romeaddro8  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
512 
                     databuf_reg(0)(8) &
513 
                     databuf_reg(1)(8) &
514 
                     databuf_reg(2)(8) &
515 
                     databuf_reg(3)(8);
516 
            romeaddro9  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
517 
                     databuf_reg(0)(9) &
518 
                     databuf_reg(1)(9) &
519 
                     databuf_reg(2)(9) &
520 
                     databuf_reg(3)(9);
521 
            romeaddro10  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
522 
                     databuf_reg(0)(10) &
523 
                     databuf_reg(1)(10) &
524 
                     databuf_reg(2)(10) &
525 
                     databuf_reg(3)(10);
526 
 
527 
            state_reg  <= SUM;
528 
          end if;
529 
 
530 
        -----------------
531 
        when others =>
532 
          state_reg  <= IDLE;
533 
      end case;
534 
    end if;
535 
  end process;
536 
 
537 
end RTL;
538 
--------------------------------------------------------------------------------
539 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.