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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2006                                --
--                                                                            --
--------------------------------------------------------------------------------
--
-- Title       : DCT1D
-- Design      : MDCT Core
-- Author      : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File        : DCT1D.VHD
-- Created     : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
--  Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.NUMERIC_STD.all;
 
library WORK;
  use WORK.MDCT_PKG.all;
 
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
        port(
                  clk          : in STD_LOGIC;
                  rst          : in std_logic;
      dcti         : in std_logic_vector(IP_W-1 downto 0);
      idv          : in STD_LOGIC;
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
 
      odv          : out STD_LOGIC;
      dcto         : out std_logic_vector(OP_W-1 downto 0);
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      ramwe        : out STD_LOGIC;
      wmemsel      : out STD_LOGIC
                );
end DCT1D;
 
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
 
  type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
 
  signal databuf_reg    : INPUT_DATA;
  signal latchbuf_reg   : INPUT_DATA;
  signal col_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal row_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rowr_reg       : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal inpcnt_reg     : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal ramdatai_s     : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
  signal ramwe_s        : STD_LOGIC;
  signal wmemsel_reg    : STD_LOGIC;
  signal stage2_reg     : STD_LOGIC;
  signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
  signal col_2_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
begin
 
  ramwe_sg:
  ramwe    <= ramwe_s;
 
  ramdatai_sg:
  ramdatai <= ramdatai_s;
 
  -- temporary
  odv_sg:
  odv      <= ramwe_s;
  dcto_sg:
  dcto     <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
 
  wmemsel_sg:
  wmemsel <= wmemsel_reg;
 
  process(clk,rst)
  begin
    if rst = '1' then
      inpcnt_reg     <= (others => '0');
      latchbuf_reg   <= (others => (others => '0'));
      databuf_reg    <= (others => (others => '0'));
      stage2_reg     <= '0';
      stage2_cnt_reg <= (others => '1');
      ramdatai_s     <= (others => '0');
      ramwe_s        <= '0';
      ramwaddro      <= (others => '0');
      col_reg        <= (others => '0');
      row_reg        <= (others => '0');
      wmemsel_reg    <= '0';
      col_2_reg      <= (others => '0');
    elsif clk = '1' and clk'event then
 
      stage2_reg     <= '0';
      ramwe_s        <= '0';
 
      --------------------------------
      -- 1st stage
      --------------------------------
      if idv = '1' then
 
        inpcnt_reg    <= inpcnt_reg + 1;
 
        -- right shift input data
        latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
        latchbuf_reg(N-1)          <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
        if inpcnt_reg = N-1 then
          -- after this sum databuf_reg is in range of -256 to 254 (min to max) 
          databuf_reg(0)  <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
          databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
          databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
          databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
          databuf_reg(4)  <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
          databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
          databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
          databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
          stage2_reg      <= '1';
        end if;
      end if;
      --------------------------------
 
      --------------------------------
      -- 2nd stage
      --------------------------------
      if stage2_cnt_reg < N then
 
        if stage2_cnt_reg(0) = '0' then
          ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
            (RESIZE(SIGNED(romedatao0),DA_W) +
            (RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
            (RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
            (RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
            (RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
            (RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
            (RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
            (RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
            (RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
                                        DA_W)(DA_W-1 downto 12));
        else
          ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
            (RESIZE(SIGNED(romodatao0),DA_W) +
            (RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
            (RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
            (RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
            (RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
            (RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
            (RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
            (RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
            (RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
                                        DA_W)(DA_W-1 downto 12));
        end if;
 
        stage2_cnt_reg <= stage2_cnt_reg + 1;
 
        -- write RAM
        ramwe_s   <= '1';
        -- reverse col/row order for transposition purpose
        ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
        -- increment column counter
        col_reg   <= col_reg + 1;
        col_2_reg <= col_2_reg + 1;
 
        -- finished processing one input row
        if col_reg = 0 then
          row_reg         <= row_reg + 1;
          -- switch to 2nd memory
          if row_reg = N - 1 then
            wmemsel_reg <= not wmemsel_reg;
            col_reg         <= (others => '0');
          end if;
        end if;
 
      end if;
 
      if stage2_reg = '1' then
        stage2_cnt_reg <= (others => '0');
        col_reg        <= (0=>'1',others => '0');
        col_2_reg      <= (others => '0');
      end if;
      ----------------------------------    
    end if;
  end process;
 
  -- read precomputed MAC results from LUT
  romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(0) &
           databuf_reg(1)(0) &
           databuf_reg(2)(0) &
           databuf_reg(3)(0);
  romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(1) &
           databuf_reg(1)(1) &
           databuf_reg(2)(1) &
           databuf_reg(3)(1);
  romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(2) &
           databuf_reg(1)(2) &
           databuf_reg(2)(2) &
           databuf_reg(3)(2);
  romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(3) &
           databuf_reg(1)(3) &
           databuf_reg(2)(3) &
           databuf_reg(3)(3);
  romeaddro4  <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(4) &
           databuf_reg(1)(4) &
           databuf_reg(2)(4) &
           databuf_reg(3)(4);
  romeaddro5  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(5) &
           databuf_reg(1)(5) &
           databuf_reg(2)(5) &
           databuf_reg(3)(5);
  romeaddro6  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(6) &
           databuf_reg(1)(6) &
           databuf_reg(2)(6) &
           databuf_reg(3)(6);
  romeaddro7  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(7) &
           databuf_reg(1)(7) &
           databuf_reg(2)(7) &
           databuf_reg(3)(7);
  romeaddro8  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(8) &
           databuf_reg(1)(8) &
           databuf_reg(2)(8) &
           databuf_reg(3)(8);
 
  -- odd
  romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(0) &
             databuf_reg(5)(0) &
             databuf_reg(6)(0) &
             databuf_reg(7)(0);
  romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(1) &
             databuf_reg(5)(1) &
             databuf_reg(6)(1) &
             databuf_reg(7)(1);
  romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(2) &
             databuf_reg(5)(2) &
             databuf_reg(6)(2) &
             databuf_reg(7)(2);
  romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(3) &
             databuf_reg(5)(3) &
             databuf_reg(6)(3) &
             databuf_reg(7)(3);
  romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(4) &
             databuf_reg(5)(4) &
             databuf_reg(6)(4) &
             databuf_reg(7)(4);
  romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(5) &
             databuf_reg(5)(5) &
             databuf_reg(6)(5) &
             databuf_reg(7)(5);
  romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(6) &
             databuf_reg(5)(6) &
             databuf_reg(6)(6) &
             databuf_reg(7)(6);
  romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(7) &
             databuf_reg(5)(7) &
             databuf_reg(6)(7) &
             databuf_reg(7)(7);
  romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
             databuf_reg(4)(8) &
             databuf_reg(5)(8) &
             databuf_reg(6)(8) &
             databuf_reg(7)(8);
 
 
end RTL;
--------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	2	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2006 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`--`
8			`-- Title : DCT1D`
9			`-- Design : MDCT Core`
10			`-- Author : Michal Krepa`
11			`--`
12			`--------------------------------------------------------------------------------`
13			`--`
14			`-- File : DCT1D.VHD`
15			`-- Created : Sat Mar 5 7:37 2006`
16			`--`
17			`--------------------------------------------------------------------------------`
18			`--`
19			`-- Description : 1D Discrete Cosine Transform (1st stage)`
20			`--`
21			`--------------------------------------------------------------------------------`
22
23
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.all;`
26			`use IEEE.NUMERIC_STD.all;`
27
28			`library WORK;`
29			`use WORK.MDCT_PKG.all;`
30
31			`--------------------------------------------------------------------------------`
32			`-- ENTITY`
33			`--------------------------------------------------------------------------------`
34			`entity DCT1D is`
35			`port(`
36			`clk : in STD_LOGIC;`
37			`rst : in std_logic;`
38			`dcti : in std_logic_vector(IP_W-1 downto 0);`
39			`idv : in STD_LOGIC;`
40			`romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
41			`romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
42			`romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
43			`romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
44			`romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
45			`romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
46			`romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
47			`romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
48			`romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
49			`romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
50			`romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
51			`romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
52			`romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
53			`romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
54			`romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
55			`romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
56			`romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
57			`romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
58
59			`odv : out STD_LOGIC;`
60			`dcto : out std_logic_vector(OP_W-1 downto 0);`
61			`romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
62			`romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
63			`romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
64			`romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
65			`romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
66			`romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
67			`romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
68			`romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
69			`romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
70			`romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
71			`romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
72			`romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
73			`romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
74			`romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
75			`romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
76			`romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
77			`romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
78			`romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
79			`ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);`
80			`ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
81			`ramwe : out STD_LOGIC;`
82	15	mikel262	`wmemsel : out STD_LOGIC`
83	2	mikel262	`);`
84			`end DCT1D;`
85
86			`--------------------------------------------------------------------------------`
87			`-- ARCHITECTURE`
88			`--------------------------------------------------------------------------------`
89			`architecture RTL of DCT1D is`
90
91			`type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);`
92
93			`signal databuf_reg : INPUT_DATA;`
94			`signal latchbuf_reg : INPUT_DATA;`
95			`signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
96			`signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
97	15	mikel262	`signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
98			`signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
99	2	mikel262	`signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
100			`signal ramwe_s : STD_LOGIC;`
101	15	mikel262	`signal wmemsel_reg : STD_LOGIC;`
102			`signal stage2_reg : STD_LOGIC;`
103			`signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);`
104			`signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
105	2	mikel262	`begin`
106
107			`ramwe_sg:`
108			`ramwe <= ramwe_s;`
109
110			`ramdatai_sg:`
111			`ramdatai <= ramdatai_s;`
112
113			`-- temporary`
114			`odv_sg:`
115			`odv <= ramwe_s;`
116			`dcto_sg:`
117			`dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;`
118
119	15	mikel262	`wmemsel_sg:`
120			`wmemsel <= wmemsel_reg;`
121
122			`process(clk,rst)`
123	2	mikel262	`begin`
124	15	mikel262	`if rst = '1' then`
125			`inpcnt_reg <= (others => '0');`
126			`latchbuf_reg <= (others => (others => '0'));`
127			`databuf_reg <= (others => (others => '0'));`
128			`stage2_reg <= '0';`
129			`stage2_cnt_reg <= (others => '1');`
130			`ramdatai_s <= (others => '0');`
131			`ramwe_s <= '0';`
132			`ramwaddro <= (others => '0');`
133			`col_reg <= (others => '0');`
134			`row_reg <= (others => '0');`
135			`wmemsel_reg <= '0';`
136			`col_2_reg <= (others => '0');`
137	2	mikel262	`elsif clk = '1' and clk'event then`
138	4	mikel262
139	15	mikel262	`stage2_reg <= '0';`
140			`ramwe_s <= '0';`
141
142			`--------------------------------`
143			`-- 1st stage`
144			`--------------------------------`
145			`if idv = '1' then`
146
147			`inpcnt_reg <= inpcnt_reg + 1;`
148
149			`-- right shift input data`
150			`latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);`
151			`latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;`
152
153			`if inpcnt_reg = N-1 then`
154			`-- after this sum databuf_reg is in range of -256 to 254 (min to max)`
155			`databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);`
156			`databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);`
157			`databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);`
158			`databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);`
159			`databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);`
160			`databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);`
161			`databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);`
162			`databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);`
163			`stage2_reg <= '1';`
164	10	mikel262	`end if;`
165	15	mikel262	`end if;`
166			`--------------------------------`
167	13	mikel262
168	15	mikel262	`--------------------------------`
169			`-- 2nd stage`
170			`--------------------------------`
171			`if stage2_cnt_reg < N then`
172	2	mikel262
173	15	mikel262	`if stage2_cnt_reg(0) = '0' then`
174	2	mikel262	`ramdatai_s <= STD_LOGIC_VECTOR(RESIZE`
175			`(RESIZE(SIGNED(romedatao0),DA_W) +`
176			`(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +`
177			`(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +`
178			`(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +`
179			`(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +`
180			`(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +`
181			`(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +`
182			`(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -`
183	13	mikel262	`(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),`
184			`DA_W)(DA_W-1 downto 12));`
185	15	mikel262	`else`
186	2	mikel262	`ramdatai_s <= STD_LOGIC_VECTOR(RESIZE`
187			`(RESIZE(SIGNED(romodatao0),DA_W) +`
188			`(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +`
189			`(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +`
190			`(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +`
191			`(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +`
192			`(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +`
193			`(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +`
194			`(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -`
195			`(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),`
196	15	mikel262	`DA_W)(DA_W-1 downto 12));`
197			`end if;`
198
199			`stage2_cnt_reg <= stage2_cnt_reg + 1;`
200
201			`-- write RAM`
202			`ramwe_s <= '1';`
203			`-- reverse col/row order for transposition purpose`
204			`ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);`
205			`-- increment column counter`
206			`col_reg <= col_reg + 1;`
207			`col_2_reg <= col_2_reg + 1;`
208
209			`-- finished processing one input row`
210			`if col_reg = 0 then`
211			`row_reg <= row_reg + 1;`
212			`-- switch to 2nd memory`
213			`if row_reg = N - 1 then`
214			`wmemsel_reg <= not wmemsel_reg;`
215	4	mikel262	`col_reg <= (others => '0');`
216	2	mikel262	`end if;`
217	15	mikel262	`end if;`
218
219			`end if;`
220
221			`if stage2_reg = '1' then`
222			`stage2_cnt_reg <= (others => '0');`
223			`col_reg <= (0=>'1',others => '0');`
224			`col_2_reg <= (others => '0');`
225			`end if;`
226			`----------------------------------`
227	2	mikel262	`end if;`
228			`end process;`
229
230	4	mikel262	`-- read precomputed MAC results from LUT`
231	15	mikel262	`romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
232	4	mikel262	`databuf_reg(0)(0) &`
233			`databuf_reg(1)(0) &`
234			`databuf_reg(2)(0) &`
235			`databuf_reg(3)(0);`
236	15	mikel262	`romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
237	4	mikel262	`databuf_reg(0)(1) &`
238			`databuf_reg(1)(1) &`
239			`databuf_reg(2)(1) &`
240			`databuf_reg(3)(1);`
241	15	mikel262	`romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
242	4	mikel262	`databuf_reg(0)(2) &`
243			`databuf_reg(1)(2) &`
244			`databuf_reg(2)(2) &`
245			`databuf_reg(3)(2);`
246	15	mikel262	`romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
247	4	mikel262	`databuf_reg(0)(3) &`
248			`databuf_reg(1)(3) &`
249			`databuf_reg(2)(3) &`
250			`databuf_reg(3)(3);`
251	15	mikel262	`romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &`
252	4	mikel262	`databuf_reg(0)(4) &`
253			`databuf_reg(1)(4) &`
254			`databuf_reg(2)(4) &`
255			`databuf_reg(3)(4);`
256	15	mikel262	`romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
257	4	mikel262	`databuf_reg(0)(5) &`
258			`databuf_reg(1)(5) &`
259			`databuf_reg(2)(5) &`
260			`databuf_reg(3)(5);`
261	15	mikel262	`romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
262	4	mikel262	`databuf_reg(0)(6) &`
263			`databuf_reg(1)(6) &`
264			`databuf_reg(2)(6) &`
265			`databuf_reg(3)(6);`
266	15	mikel262	`romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
267	4	mikel262	`databuf_reg(0)(7) &`
268			`databuf_reg(1)(7) &`
269			`databuf_reg(2)(7) &`
270			`databuf_reg(3)(7);`
271	15	mikel262	`romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
272	4	mikel262	`databuf_reg(0)(8) &`
273			`databuf_reg(1)(8) &`
274			`databuf_reg(2)(8) &`
275	15	mikel262	`databuf_reg(3)(8);`
276	4	mikel262
277			`-- odd`
278			`romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
279			`databuf_reg(4)(0) &`
280			`databuf_reg(5)(0) &`
281			`databuf_reg(6)(0) &`
282			`databuf_reg(7)(0);`
283			`romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
284			`databuf_reg(4)(1) &`
285			`databuf_reg(5)(1) &`
286			`databuf_reg(6)(1) &`
287			`databuf_reg(7)(1);`
288			`romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
289			`databuf_reg(4)(2) &`
290			`databuf_reg(5)(2) &`
291			`databuf_reg(6)(2) &`
292			`databuf_reg(7)(2);`
293			`romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
294			`databuf_reg(4)(3) &`
295			`databuf_reg(5)(3) &`
296			`databuf_reg(6)(3) &`
297			`databuf_reg(7)(3);`
298			`romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
299			`databuf_reg(4)(4) &`
300			`databuf_reg(5)(4) &`
301			`databuf_reg(6)(4) &`
302			`databuf_reg(7)(4);`
303			`romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
304			`databuf_reg(4)(5) &`
305			`databuf_reg(5)(5) &`
306			`databuf_reg(6)(5) &`
307			`databuf_reg(7)(5);`
308			`romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
309			`databuf_reg(4)(6) &`
310			`databuf_reg(5)(6) &`
311			`databuf_reg(6)(6) &`
312			`databuf_reg(7)(6);`
313			`romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
314			`databuf_reg(4)(7) &`
315			`databuf_reg(5)(7) &`
316			`databuf_reg(6)(7) &`
317			`databuf_reg(7)(7);`
318			`romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
319			`databuf_reg(4)(8) &`
320			`databuf_reg(5)(8) &`
321			`databuf_reg(6)(8) &`
322			`databuf_reg(7)(8);`
323	15	mikel262
324	4	mikel262
325	2	mikel262	`end RTL;`
326			`--------------------------------------------------------------------------------`

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