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1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : DCT2D
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
--
12 
--------------------------------------------------------------------------------
13 
--
14 
-- File        : DCT2D.VHD
15 
-- Created     : Sat Mar 28 22:32 2006
16 
--
17 
--------------------------------------------------------------------------------
18 
--
19 
--  Description : 1D Discrete Cosine Transform (second stage)
20 
--
21 
--------------------------------------------------------------------------------
22 
 
23 
 
24 
library IEEE;
25 
  use IEEE.STD_LOGIC_1164.all;
26 
  use ieee.numeric_std.all;
27 
 
28 
library WORK;
29 
  use WORK.MDCT_PKG.all;
30 
 
31 
entity DCT2D is
32 
        port(
33 
      clk          : in STD_LOGIC;
34 
      rst          : in std_logic;
35 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
36 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
37 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
38 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
39 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
40 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
41 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
42 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
43 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
44 
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
45 
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
46 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
47 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
48 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
49 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
50 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
51 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
52 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
53 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
54 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
55 
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
56 
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
57 
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
58 
      reqrdfail    : in STD_LOGIC;
59 
      dataready    : in STD_LOGIC;
60 
 
61 
      odv          : out STD_LOGIC;
62 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
63 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
64 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
65 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
66 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
67 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
68 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
69 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
70 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
71 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
72 
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
73 
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
74 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
75 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
76 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
77 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
78 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
79 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
80 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
81 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
82 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
83 
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
84 
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
85 
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
86 
      requestrd    : out STD_LOGIC;
87 
      releaserd    : out STD_LOGIC
88 
 
89 
                );
90 
end DCT2D;
91 
 
92 
architecture RTL of DCT2D is
93 
 
94 
  type STATE2_T is
95 
  (
96 
    IDLE,
97 
    GET_ROM,
98 
    SUM,
99 
    WRITE_ODD
100 
  );
101 
 
102 
  type ISTATE2_T is
103 
  (
104 
    IDLE_I,
105 7 mikel262 
    ACQUIRE_1ROW
106 2 mikel262 
  );
107 
 
108 
  type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
109 
 
110 
  signal databuf_reg    : input_data2;
111 
  signal latchbuf_reg   : input_data2;
112 
  signal col_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
113 
  signal row_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
114 
  signal state_reg      : STATE2_T;
115 
  signal istate_reg     : ISTATE2_T;
116 
  signal cnt_reg        : UNSIGNED(3 downto 0);
117 
  signal latch_done_reg : STD_LOGIC;
118 
  signal rowram_reg     : UNSIGNED(RAMADRR_W/2-1 downto 0);
119 
  signal colram_reg     : UNSIGNED(RAMADRR_W/2 downto 0);
120 
  signal requestrd_reg  : STD_LOGIC;
121 
  signal releaserd_reg  : STD_LOGIC;
122 
  signal completed_reg  : STD_LOGIC;
123 
  signal col_tmp_reg    : UNSIGNED(RAMADRR_W/2-1 downto 0);
124 
 
125 
begin
126 
 
127 
  ramraddro_sg:
128 
  ramraddro  <= STD_LOGIC_VECTOR(rowram_reg & colram_reg(2 downto 0));
129 
 
130 
  requestrd_sg:
131 
  requestrd  <= requestrd_reg;
132 
 
133 
  releaserd_sg:
134 
  releaserd  <= releaserd_reg;
135 
 
136 
  GET_PROC : process(rst,clk)
137 
  begin
138 
    if rst = '1' then
139 
      rowram_reg     <= (others => '0');
140 
      colram_reg     <= (others => '0');
141 
      latchbuf_reg   <= (others => (others => '0'));
142 
      istate_reg     <= IDLE_I;
143 
      latch_done_reg <= '0';
144 
      completed_reg  <= '0';
145 
      requestrd_reg  <= '0';
146 
      releaserd_reg  <= '0';
147 13 mikel262 
      databuf_reg  <= (others => (others => '0'));
148 2 mikel262 
    elsif clk = '1' and clk'event then
149 
      case istate_reg is
150 
 
151 
        ----------------------
152 
        -- IDLE
153 
        ----------------------
154 
        when IDLE_I =>
155 13 mikel262 
          -- one of ram buffers has new data, process it
156 2 mikel262 
          if dataready = '1' then
157 
            requestrd_reg <= '1';
158 
          end if;
159 
          -- give 1T delay needed by DBUFCTL
160 
          if requestrd_reg = '1' then
161 
            requestrd_reg <= '0';
162 
            istate_reg <= ACQUIRE_1ROW;
163 13 mikel262 
            -- to account for 1T RAM delay, increment RAM address counter
164 
            colram_reg <= (0=>'1',others => '0');
165 2 mikel262 
          end if;
166 
 
167 
        ----------------------
168 
        -- latch input data to barrel shifter
169 
        ----------------------
170 
        when ACQUIRE_1ROW =>
171 
 
172 7 mikel262 
          if latch_done_reg = '0' then
173 
            -- not starting from zero b/c of RAM 1T delay
174 
            if colram_reg /= 0 then
175 
              -- right shift input data
176 
              latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
177 
              latchbuf_reg(N-1)          <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
178 
            end if;
179 
 
180 
            colram_reg  <= colram_reg + 1;
181 2 mikel262 
 
182 7 mikel262 
            -- not N-1
183 
            if colram_reg = N then
184 
              -- finished reading 64 point 1D DCT from RAM
185 
              if rowram_reg = N-1 then
186 
                -- release memory
187 
                releaserd_reg <= '1';
188 
                completed_reg <= '1';
189 
              end if;
190 13 mikel262 
              colram_reg  <= ( others => '0');
191 7 mikel262 
              rowram_reg  <= rowram_reg + 1;
192 
              -- 8 point input latched
193 
              latch_done_reg <= '1';
194 13 mikel262 
              -- after this sum databuf_reg is in range of -256 to 254 (min to max)
195 
              databuf_reg(0)  <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
196 
              databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
197 
              databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
198 
              databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
199 
              databuf_reg(4)  <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
200 
              databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
201 
              databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
202 
              databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
203 7 mikel262 
            end if;
204 2 mikel262 
 
205 7 mikel262 
            -- failure to allocate memory buffer
206 
            -- should never happen?
207 
            if reqrdfail = '1' then
208 
              istate_reg <= IDLE_I;
209 
            end if;
210 
          else
211 
            releaserd_reg <= '0';
212 
            -- wait until DCT1D_PROC process 1D DCT computation
213 
            -- before latching new 8 input words
214 
            if state_reg = IDLE then
215 
              latch_done_reg  <= '0';
216 
              if completed_reg = '1' then
217 
                completed_reg <= '0';
218 13 mikel262 
                colram_reg    <= (others => '0');
219 7 mikel262 
                istate_reg    <= IDLE_I;
220 
              else
221 
                istate_reg <= ACQUIRE_1ROW;
222 13 mikel262 
                -- to account for 1T RAM delay, increment RAM address counter
223 
                colram_reg <= (0=>'1',others => '0');
224 7 mikel262 
              end if;
225 2 mikel262 
            end if;
226 7 mikel262 
          end if;
227 2 mikel262 
 
228 
        when others =>
229 
          istate_reg <= IDLE_I;
230 
      end case;
231 
    end if;
232 
  end process;
233 
 
234 
 
235 
  DCT1D_PROC: process(rst, clk)
236 
  begin
237 
    if rst = '1' then
238 
      col_reg      <= (others => '0');
239 
      row_reg      <= (others => '0');
240 
      state_reg    <= IDLE;
241 
      cnt_reg      <= (others => '0');
242 
      odv           <= '0';
243 
      dcto          <= (others => '0');
244 
      col_tmp_reg   <= (others => '0');
245 
    elsif rising_edge(clk) then
246 
 
247 
      case state_reg is
248 
 
249 
        ----------------------
250 
        -- wait for input data
251 
        ----------------------
252 
        when IDLE =>
253 
 
254 
          odv <= '0';
255 
          -- wait until 8 input words are latched in latchbuf_reg
256 
          -- by GET_PROC
257 
          if latch_done_reg = '1' then
258 13 mikel262 
 
259 
            state_reg   <= SUM;
260 2 mikel262 
          end if;
261 
 
262 
        ----------------------
263 
        -- get MAC results from ROM even and ROM odd memories
264 
        ----------------------
265 
        when GET_ROM =>
266 
 
267 4 mikel262 
           odv <= '0';
268 2 mikel262 
 
269 
           state_reg <= SUM;
270 
 
271 
        ---------------------
272 
        -- do distributed arithmetic sum on even part,
273 
        -- write even part to RAM
274 
        ---------------------
275 
        when SUM =>
276 
 
277 
          -- (a0 +
278 
          -- a1*2 +
279 
          -- (a2 + a3*2)*4 +
280 
          -- a4 * 2^4 +
281 
          -- a5*2 * 2^4 +
282 
          -- (a6 +
283 
          -- a7*2)*2^6 )/
284 
          -- 2^11
285 
          dcto <= STD_LOGIC_VECTOR(RESIZE
286 
            (RESIZE(SIGNED(romedatao0),DA2_W) +
287 
            (RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
288 
            (RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +
289 
            (RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
290 
            (RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
291 
            (RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
292 
            (RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +
293 
            (RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
294 
            (RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
295 
            (RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
296 
            (RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
297 
            DA2_W)(DA2_W-1 downto 12));
298 
 
299 
          -- write even part
300 
          odv   <= '1';
301 
 
302 
          col_reg <= col_reg + 1;
303 
          col_tmp_reg <= col_reg + 2;
304 4 mikel262 
 
305 2 mikel262 
          state_reg <= WRITE_ODD;
306 
 
307 
        ---------------------
308 
        -- do distributed arithmetic sum on odd part,
309 
        -- write odd part to RAM
310 
        ---------------------
311 
        when WRITE_ODD =>
312 
 
313 
          dcto <= STD_LOGIC_VECTOR(RESIZE
314 
            (RESIZE(SIGNED(romodatao0),DA2_W) +
315 
            (RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
316 
            (RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +
317 
            (RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
318 
            (RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
319 
            (RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
320 
            (RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +
321 
            (RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
322 
            (RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
323 
            (RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
324 
            (RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
325 
            DA2_W)(DA2_W-1 downto 12));
326 
 
327 
          col_reg <= col_reg + 1;
328 4 mikel262 
          col_tmp_reg <= col_reg + 1;
329 2 mikel262 
 
330 
          -- finished processing one input row (1 x N)
331 
          if col_reg = N - 1 then
332 
            row_reg <= row_reg + 1;
333 
            col_reg <= (others => '0');
334 4 mikel262 
            col_tmp_reg <= (others => '0');
335 2 mikel262 
            state_reg  <= IDLE;
336 
          else
337 
            state_reg  <= SUM;
338 
          end if;
339 
 
340 
        -----------------
341 
        when others =>
342 
          state_reg  <= IDLE;
343 
      end case;
344 
    end if;
345 
  end process;
346 4 mikel262 
 
347 
  -- read precomputed MAC results from LUT
348 
  romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
349 
           databuf_reg(0)(0) &
350 
           databuf_reg(1)(0) &
351 
           databuf_reg(2)(0) &
352 
           databuf_reg(3)(0);
353 
  romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
354 
           databuf_reg(0)(1) &
355 
           databuf_reg(1)(1) &
356 
           databuf_reg(2)(1) &
357 
           databuf_reg(3)(1);
358 
  romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
359 
           databuf_reg(0)(2) &
360 
           databuf_reg(1)(2) &
361 
           databuf_reg(2)(2) &
362 
           databuf_reg(3)(2);
363 
  romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
364 
           databuf_reg(0)(3) &
365 
           databuf_reg(1)(3) &
366 
           databuf_reg(2)(3) &
367 
           databuf_reg(3)(3);
368 
  romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
369 
           databuf_reg(0)(4) &
370 
           databuf_reg(1)(4) &
371 
           databuf_reg(2)(4) &
372 
           databuf_reg(3)(4);
373 
  romeaddro5  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
374 
           databuf_reg(0)(5) &
375 
           databuf_reg(1)(5) &
376 
           databuf_reg(2)(5) &
377 
           databuf_reg(3)(5);
378 
  romeaddro6  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
379 
           databuf_reg(0)(6) &
380 
           databuf_reg(1)(6) &
381 
           databuf_reg(2)(6) &
382 
           databuf_reg(3)(6);
383 
  romeaddro7  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
384 
           databuf_reg(0)(7) &
385 
           databuf_reg(1)(7) &
386 
           databuf_reg(2)(7) &
387 
           databuf_reg(3)(7);
388 
  romeaddro8  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
389 
           databuf_reg(0)(8) &
390 
           databuf_reg(1)(8) &
391 
           databuf_reg(2)(8) &
392 
           databuf_reg(3)(8);
393 
  romeaddro9  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
394 
           databuf_reg(0)(9) &
395 
           databuf_reg(1)(9) &
396 
           databuf_reg(2)(9) &
397 
           databuf_reg(3)(9);
398 
  romeaddro10  <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
399 
           databuf_reg(0)(10) &
400 
           databuf_reg(1)(10) &
401 
           databuf_reg(2)(10) &
402 
           databuf_reg(3)(10);
403 
  -- odd
404 
  romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
405 
            databuf_reg(4)(0) &
406 
            databuf_reg(5)(0) &
407 
            databuf_reg(6)(0) &
408 
            databuf_reg(7)(0);
409 
  romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
410 
            databuf_reg(4)(1) &
411 
            databuf_reg(5)(1) &
412 
            databuf_reg(6)(1) &
413 
            databuf_reg(7)(1);
414 
  romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
415 
            databuf_reg(4)(2) &
416 
            databuf_reg(5)(2) &
417 
            databuf_reg(6)(2) &
418 
            databuf_reg(7)(2);
419 
  romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
420 
            databuf_reg(4)(3) &
421 
            databuf_reg(5)(3) &
422 
            databuf_reg(6)(3) &
423 
            databuf_reg(7)(3);
424 
  romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
425 
            databuf_reg(4)(4) &
426 
            databuf_reg(5)(4) &
427 
            databuf_reg(6)(4) &
428 
            databuf_reg(7)(4);
429 
  romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
430 
            databuf_reg(4)(5) &
431 
            databuf_reg(5)(5) &
432 
            databuf_reg(6)(5) &
433 
            databuf_reg(7)(5);
434 
  romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
435 
            databuf_reg(4)(6) &
436 
            databuf_reg(5)(6) &
437 
            databuf_reg(6)(6) &
438 
            databuf_reg(7)(6);
439 
  romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
440 
            databuf_reg(4)(7) &
441 
            databuf_reg(5)(7) &
442 
            databuf_reg(6)(7) &
443 
            databuf_reg(7)(7);
444 
  romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
445 
            databuf_reg(4)(8) &
446 
            databuf_reg(5)(8) &
447 
            databuf_reg(6)(8) &
448 
            databuf_reg(7)(8);
449 
  romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
450 
            databuf_reg(4)(9) &
451 
            databuf_reg(5)(9) &
452 
            databuf_reg(6)(9) &
453 
            databuf_reg(7)(9);
454 
  romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
455 
            databuf_reg(4)(10) &
456 
            databuf_reg(5)(10) &
457 
            databuf_reg(6)(10) &
458 
            databuf_reg(7)(10);
459 2 mikel262 
 
460 
end RTL;
461 
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462 
 

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