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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2006                                --
--                                                                            --
--------------------------------------------------------------------------------
--
-- Title       : DCT2D
-- Design      : MDCT Core
-- Author      : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File        : DCT2D.VHD
-- Created     : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
--  Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use ieee.numeric_std.all;
 
library WORK;
  use WORK.MDCT_PKG.all;
 
entity DCT2D is
        port(
      clk          : in STD_LOGIC;
      rst          : in std_logic;
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      dataready    : in STD_LOGIC;
 
      odv          : out STD_LOGIC;
      dcto         : out std_logic_vector(OP_W-1 downto 0);
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
      rmemsel      : out STD_LOGIC;
      datareadyack : out STD_LOGIC
 
                );
end DCT2D;
 
architecture RTL of DCT2D is
 
  type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
 
  signal databuf_reg    : input_data2;
  signal latchbuf_reg   : input_data2;
  signal col_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal row_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal colram_reg     : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rowram_reg     : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal colr_reg       : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rowr_reg       : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rmemsel_reg    : STD_LOGIC;
  signal stage1_reg     : STD_LOGIC;
  signal stage2_reg     : STD_LOGIC;
  signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
  signal dataready_2_reg : STD_LOGIC;
 
begin
 
  ramraddro_sg:
  ramraddro  <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
 
  rmemsel_sg:
  rmemsel    <= rmemsel_reg;
 
  process(clk)
  begin
    if clk='1' and clk'event then
      if rst = '1' then
        stage2_cnt_reg       <= (others => '1');
        rmemsel_reg          <= '0';
        stage1_reg           <= '0';
        stage2_reg           <= '0';
        colram_reg           <= (others => '0');
        rowram_reg           <= (others => '0');
        col_reg              <= (others => '0');
        row_reg              <= (others => '0');
        latchbuf_reg         <= (others => (others => '0'));
        databuf_reg          <= (others => (others => '0'));
        dcto                 <= (others => '0');
        odv                  <= '0';
        colr_reg             <= (others => '0');
        rowr_reg             <= (others => '0');
        dataready_2_reg      <= '0';
      else
 
        stage2_reg    <= '0';
        odv           <= '0';
        datareadyack  <= '0';
 
        dataready_2_reg <= dataready;
 
        ----------------------------------
        -- read DCT 1D to barrel shifer
        ----------------------------------
        if stage1_reg = '1' then
 
          -- right shift input data
          latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
          latchbuf_reg(N-1)          <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
 
          colram_reg  <= colram_reg + 1;
          colr_reg    <= colr_reg + 1;
 
          if colram_reg = N-2 then
            rowr_reg <= rowr_reg + 1;
          end if;
 
          if colram_reg = N-1 then
            rowram_reg <= rowram_reg + 1;
            if rowram_reg = N-1 then
              stage1_reg    <= '0';
              colr_reg      <= (others => '0');
              -- release memory
              rmemsel_reg    <= not rmemsel_reg;
            end if;
 
            -- after this sum databuf_reg is in range of -256 to 254 (min to max)
            databuf_reg(0)  <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
            databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
            databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
            databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
            databuf_reg(4)  <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
            databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
            databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
            databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
 
            -- 8 point input latched
            stage2_reg      <= '1';
          end if;
        end if;
 
        --------------------------------
        -- 2nd stage
        --------------------------------
        if stage2_cnt_reg < N then
 
          if stage2_cnt_reg(0) = '0' then
            dcto <= STD_LOGIC_VECTOR(RESIZE
              (RESIZE(SIGNED(romedatao0),DA2_W) +
              (RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
              (RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +
              (RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
              (RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
              (RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
              (RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +
              (RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
              (RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
              (RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
              (RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
              DA2_W)(DA2_W-1 downto 12));
          else
            dcto <= STD_LOGIC_VECTOR(RESIZE
              (RESIZE(SIGNED(romodatao0),DA2_W) +
              (RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
              (RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +
              (RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
              (RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
              (RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
              (RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +
              (RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
              (RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
              (RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
              (RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
              DA2_W)(DA2_W-1 downto 12));
          end if;
 
          stage2_cnt_reg <= stage2_cnt_reg + 1;
 
          -- write RAM
          odv       <= '1';
 
          -- increment column counter
          col_reg   <= col_reg + 1;
 
          -- finished processing one input row
          if col_reg = N - 1 then
            row_reg         <= row_reg + 1;
          end if;
        end if;
 
        if stage2_reg = '1' then
          stage2_cnt_reg <= (others => '0');
          col_reg        <= (0=>'1',others => '0');
        end if;
        --------------------------------
 
        ----------------------------------
        -- wait for new data
        ----------------------------------
        -- one of ram buffers has new data, process it
        if dataready = '1' and dataready_2_reg = '0'  then
          stage1_reg    <= '1';
          -- to account for 1T RAM delay, increment RAM address counter
          colram_reg    <= (others => '0');
          colr_reg      <= (0=>'1',others => '0');
          datareadyack  <= '1';
        end if;
        ----------------------------------
 
      end if;
    end if;
  end process;
 
  -- read precomputed MAC results from LUT
  romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(0) &
           databuf_reg(1)(0) &
           databuf_reg(2)(0) &
           databuf_reg(3)(0);
  romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(1) &
           databuf_reg(1)(1) &
           databuf_reg(2)(1) &
           databuf_reg(3)(1);
  romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(2) &
           databuf_reg(1)(2) &
           databuf_reg(2)(2) &
           databuf_reg(3)(2);
  romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(3) &
           databuf_reg(1)(3) &
           databuf_reg(2)(3) &
           databuf_reg(3)(3);
  romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(4) &
           databuf_reg(1)(4) &
           databuf_reg(2)(4) &
           databuf_reg(3)(4);
  romeaddro5  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(5) &
           databuf_reg(1)(5) &
           databuf_reg(2)(5) &
           databuf_reg(3)(5);
  romeaddro6  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(6) &
           databuf_reg(1)(6) &
           databuf_reg(2)(6) &
           databuf_reg(3)(6);
  romeaddro7  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(7) &
           databuf_reg(1)(7) &
           databuf_reg(2)(7) &
           databuf_reg(3)(7);
  romeaddro8  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(8) &
           databuf_reg(1)(8) &
           databuf_reg(2)(8) &
           databuf_reg(3)(8);
  romeaddro9  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(9) &
           databuf_reg(1)(9) &
           databuf_reg(2)(9) &
           databuf_reg(3)(9);
  romeaddro10  <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
           databuf_reg(0)(10) &
           databuf_reg(1)(10) &
           databuf_reg(2)(10) &
           databuf_reg(3)(10);
  -- odd
  romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(0) &
            databuf_reg(5)(0) &
            databuf_reg(6)(0) &
            databuf_reg(7)(0);
  romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(1) &
            databuf_reg(5)(1) &
            databuf_reg(6)(1) &
            databuf_reg(7)(1);
  romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(2) &
            databuf_reg(5)(2) &
            databuf_reg(6)(2) &
            databuf_reg(7)(2);
  romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(3) &
            databuf_reg(5)(3) &
            databuf_reg(6)(3) &
            databuf_reg(7)(3);
  romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(4) &
            databuf_reg(5)(4) &
            databuf_reg(6)(4) &
            databuf_reg(7)(4);
  romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(5) &
            databuf_reg(5)(5) &
            databuf_reg(6)(5) &
            databuf_reg(7)(5);
  romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(6) &
            databuf_reg(5)(6) &
            databuf_reg(6)(6) &
            databuf_reg(7)(6);
  romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(7) &
            databuf_reg(5)(7) &
            databuf_reg(6)(7) &
            databuf_reg(7)(7);
  romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(8) &
            databuf_reg(5)(8) &
            databuf_reg(6)(8) &
            databuf_reg(7)(8);
  romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(9) &
            databuf_reg(5)(9) &
            databuf_reg(6)(9) &
            databuf_reg(7)(9);
  romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
            databuf_reg(4)(10) &
            databuf_reg(5)(10) &
            databuf_reg(6)(10) &
            databuf_reg(7)(10);
 
end RTL;
--------------------------------------------------------------------------------
 

Line No.	Rev	Author	Line
1	2	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2006 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`--`
8			`-- Title : DCT2D`
9			`-- Design : MDCT Core`
10			`-- Author : Michal Krepa`
11			`--`
12			`--------------------------------------------------------------------------------`
13			`--`
14			`-- File : DCT2D.VHD`
15			`-- Created : Sat Mar 28 22:32 2006`
16			`--`
17			`--------------------------------------------------------------------------------`
18			`--`
19			`-- Description : 1D Discrete Cosine Transform (second stage)`
20			`--`
21			`--------------------------------------------------------------------------------`
22
23
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.all;`
26			`use ieee.numeric_std.all;`
27
28			`library WORK;`
29			`use WORK.MDCT_PKG.all;`
30
31			`entity DCT2D is`
32			`port(`
33			`clk : in STD_LOGIC;`
34			`rst : in std_logic;`
35			`romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
36			`romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
37			`romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
38			`romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
39			`romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
40			`romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
41			`romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
42			`romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
43			`romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
44			`romedatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
45			`romedatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
46			`romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
47			`romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
48			`romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
49			`romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
50			`romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
51			`romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
52			`romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
53			`romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
54			`romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
55			`romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
56			`romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);`
57			`ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
58			`dataready : in STD_LOGIC;`
59
60			`odv : out STD_LOGIC;`
61			`dcto : out std_logic_vector(OP_W-1 downto 0);`
62			`romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
63			`romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
64			`romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
65			`romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
66			`romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
67			`romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
68			`romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
69			`romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
70			`romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
71			`romeaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
72			`romeaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
73			`romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
74			`romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
75			`romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
76			`romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
77			`romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
78			`romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
79			`romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
80			`romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
81			`romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
82			`romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
83			`romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);`
84			`ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);`
85	15	mikel262	`rmemsel : out STD_LOGIC;`
86			`datareadyack : out STD_LOGIC`
87	2	mikel262
88			`);`
89			`end DCT2D;`
90
91			`architecture RTL of DCT2D is`
92
93			`type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);`
94
95			`signal databuf_reg : input_data2;`
96			`signal latchbuf_reg : input_data2;`
97			`signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
98			`signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
99	15	mikel262	`signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
100	2	mikel262	`signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
101	15	mikel262	`signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
102			`signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
103			`signal rmemsel_reg : STD_LOGIC;`
104			`signal stage1_reg : STD_LOGIC;`
105			`signal stage2_reg : STD_LOGIC;`
106			`signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);`
107			`signal dataready_2_reg : STD_LOGIC;`
108	2	mikel262
109			`begin`
110
111			`ramraddro_sg:`
112	15	mikel262	`ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);`
113	2	mikel262
114	15	mikel262	`rmemsel_sg:`
115			`rmemsel <= rmemsel_reg;`
116	2	mikel262
117	18	mikel262	`process(clk)`
118	15	mikel262	`begin`
119	18	mikel262	`if clk='1' and clk'event then`
120			`if rst = '1' then`
121			`stage2_cnt_reg <= (others => '1');`
122			`rmemsel_reg <= '0';`
123			`stage1_reg <= '0';`
124			`stage2_reg <= '0';`
125			`colram_reg <= (others => '0');`
126			`rowram_reg <= (others => '0');`
127			`col_reg <= (others => '0');`
128			`row_reg <= (others => '0');`
129			`latchbuf_reg <= (others => (others => '0'));`
130			`databuf_reg <= (others => (others => '0'));`
131			`dcto <= (others => '0');`
132			`odv <= '0';`
133			`colr_reg <= (others => '0');`
134			`rowr_reg <= (others => '0');`
135			`dataready_2_reg <= '0';`
136			`else`
137	2	mikel262
138	18	mikel262	`stage2_reg <= '0';`
139			`odv <= '0';`
140			`datareadyack <= '0';`
141
142			`dataready_2_reg <= dataready;`
143
144			`----------------------------------`
145			`-- read DCT 1D to barrel shifer`
146			`----------------------------------`
147			`if stage1_reg = '1' then`
148
149			`-- right shift input data`
150			`latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);`
151			`latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
152
153			`colram_reg <= colram_reg + 1;`
154			`colr_reg <= colr_reg + 1;`
155
156			`if colram_reg = N-2 then`
157			`rowr_reg <= rowr_reg + 1;`
158			`end if;`
159
160			`if colram_reg = N-1 then`
161			`rowram_reg <= rowram_reg + 1;`
162			`if rowram_reg = N-1 then`
163			`stage1_reg <= '0';`
164			`colr_reg <= (others => '0');`
165			`-- release memory`
166			`rmemsel_reg <= not rmemsel_reg;`
167			`end if;`
168
169			`-- after this sum databuf_reg is in range of -256 to 254 (min to max)`
170			`databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
171			`databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);`
172			`databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);`
173			`databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);`
174			`databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
175			`databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);`
176			`databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);`
177			`databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);`
178
179			`-- 8 point input latched`
180			`stage2_reg <= '1';`
181			`end if;`
182			`end if;`
183	15	mikel262
184	18	mikel262	`--------------------------------`
185			`-- 2nd stage`
186			`--------------------------------`
187			`if stage2_cnt_reg < N then`
188
189			`if stage2_cnt_reg(0) = '0' then`
190			`dcto <= STD_LOGIC_VECTOR(RESIZE`
191			`(RESIZE(SIGNED(romedatao0),DA2_W) +`
192			`(RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +`
193			`(RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +`
194			`(RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +`
195			`(RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +`
196			`(RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +`
197			`(RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +`
198			`(RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +`
199			`(RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +`
200			`(RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -`
201			`(RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),`
202			`DA2_W)(DA2_W-1 downto 12));`
203			`else`
204			`dcto <= STD_LOGIC_VECTOR(RESIZE`
205			`(RESIZE(SIGNED(romodatao0),DA2_W) +`
206			`(RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +`
207			`(RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +`
208			`(RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +`
209			`(RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +`
210			`(RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +`
211			`(RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +`
212			`(RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +`
213			`(RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +`
214			`(RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -`
215			`(RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),`
216			`DA2_W)(DA2_W-1 downto 12));`
217	2	mikel262	`end if;`
218	15	mikel262
219	18	mikel262	`stage2_cnt_reg <= stage2_cnt_reg + 1;`
220	15	mikel262
221	18	mikel262	`-- write RAM`
222			`odv <= '1';`
223
224			`-- increment column counter`
225			`col_reg <= col_reg + 1;`
226
227			`-- finished processing one input row`
228			`if col_reg = N - 1 then`
229			`row_reg <= row_reg + 1;`
230			`end if;`
231			`end if;`
232
233			`if stage2_reg = '1' then`
234			`stage2_cnt_reg <= (others => '0');`
235			`col_reg <= (0=>'1',others => '0');`
236			`end if;`
237			`--------------------------------`
238	2	mikel262
239	18	mikel262	`----------------------------------`
240			`-- wait for new data`
241			`----------------------------------`
242			`-- one of ram buffers has new data, process it`
243			`if dataready = '1' and dataready_2_reg = '0' then`
244			`stage1_reg <= '1';`
245			`-- to account for 1T RAM delay, increment RAM address counter`
246			`colram_reg <= (others => '0');`
247			`colr_reg <= (0=>'1',others => '0');`
248			`datareadyack <= '1';`
249	15	mikel262	`end if;`
250	18	mikel262	`----------------------------------`
251
252	15	mikel262	`end if;`
253	2	mikel262	`end if;`
254	15	mikel262	`end process;`
255	4	mikel262
256			`-- read precomputed MAC results from LUT`
257	15	mikel262	`romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
258	4	mikel262	`databuf_reg(0)(0) &`
259			`databuf_reg(1)(0) &`
260			`databuf_reg(2)(0) &`
261			`databuf_reg(3)(0);`
262	15	mikel262	`romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
263	4	mikel262	`databuf_reg(0)(1) &`
264			`databuf_reg(1)(1) &`
265			`databuf_reg(2)(1) &`
266			`databuf_reg(3)(1);`
267	15	mikel262	`romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
268	4	mikel262	`databuf_reg(0)(2) &`
269			`databuf_reg(1)(2) &`
270			`databuf_reg(2)(2) &`
271			`databuf_reg(3)(2);`
272	15	mikel262	`romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
273	4	mikel262	`databuf_reg(0)(3) &`
274			`databuf_reg(1)(3) &`
275			`databuf_reg(2)(3) &`
276			`databuf_reg(3)(3);`
277	15	mikel262	`romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
278	4	mikel262	`databuf_reg(0)(4) &`
279			`databuf_reg(1)(4) &`
280			`databuf_reg(2)(4) &`
281			`databuf_reg(3)(4);`
282	15	mikel262	`romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
283	4	mikel262	`databuf_reg(0)(5) &`
284			`databuf_reg(1)(5) &`
285			`databuf_reg(2)(5) &`
286			`databuf_reg(3)(5);`
287	15	mikel262	`romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
288	4	mikel262	`databuf_reg(0)(6) &`
289			`databuf_reg(1)(6) &`
290			`databuf_reg(2)(6) &`
291			`databuf_reg(3)(6);`
292	15	mikel262	`romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
293	4	mikel262	`databuf_reg(0)(7) &`
294			`databuf_reg(1)(7) &`
295			`databuf_reg(2)(7) &`
296			`databuf_reg(3)(7);`
297	15	mikel262	`romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
298	4	mikel262	`databuf_reg(0)(8) &`
299			`databuf_reg(1)(8) &`
300			`databuf_reg(2)(8) &`
301			`databuf_reg(3)(8);`
302	15	mikel262	`romeaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
303	4	mikel262	`databuf_reg(0)(9) &`
304			`databuf_reg(1)(9) &`
305			`databuf_reg(2)(9) &`
306			`databuf_reg(3)(9);`
307	15	mikel262	`romeaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
308	4	mikel262	`databuf_reg(0)(10) &`
309			`databuf_reg(1)(10) &`
310			`databuf_reg(2)(10) &`
311			`databuf_reg(3)(10);`
312			`-- odd`
313			`romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
314			`databuf_reg(4)(0) &`
315			`databuf_reg(5)(0) &`
316			`databuf_reg(6)(0) &`
317			`databuf_reg(7)(0);`
318			`romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
319			`databuf_reg(4)(1) &`
320			`databuf_reg(5)(1) &`
321			`databuf_reg(6)(1) &`
322			`databuf_reg(7)(1);`
323			`romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
324			`databuf_reg(4)(2) &`
325			`databuf_reg(5)(2) &`
326			`databuf_reg(6)(2) &`
327			`databuf_reg(7)(2);`
328			`romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
329			`databuf_reg(4)(3) &`
330			`databuf_reg(5)(3) &`
331			`databuf_reg(6)(3) &`
332			`databuf_reg(7)(3);`
333			`romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
334			`databuf_reg(4)(4) &`
335			`databuf_reg(5)(4) &`
336			`databuf_reg(6)(4) &`
337			`databuf_reg(7)(4);`
338			`romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
339			`databuf_reg(4)(5) &`
340			`databuf_reg(5)(5) &`
341			`databuf_reg(6)(5) &`
342			`databuf_reg(7)(5);`
343			`romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
344			`databuf_reg(4)(6) &`
345			`databuf_reg(5)(6) &`
346			`databuf_reg(6)(6) &`
347			`databuf_reg(7)(6);`
348			`romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
349			`databuf_reg(4)(7) &`
350			`databuf_reg(5)(7) &`
351			`databuf_reg(6)(7) &`
352			`databuf_reg(7)(7);`
353			`romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
354			`databuf_reg(4)(8) &`
355			`databuf_reg(5)(8) &`
356			`databuf_reg(6)(8) &`
357			`databuf_reg(7)(8);`
358			`romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
359			`databuf_reg(4)(9) &`
360			`databuf_reg(5)(9) &`
361			`databuf_reg(6)(9) &`
362			`databuf_reg(7)(9);`
363			`romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
364			`databuf_reg(4)(10) &`
365			`databuf_reg(5)(10) &`
366			`databuf_reg(6)(10) &`
367			`databuf_reg(7)(10);`
368	2	mikel262
369			`end RTL;`
370			`--------------------------------------------------------------------------------`
371

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