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[/] [mdct/] [trunk/] [source/] [MDCT.VHD] - Blame information for rev 11

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Line No. Rev Author Line
1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : DCT
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
-- Company     : None
12 
--
13 
--------------------------------------------------------------------------------
14 
--
15 
-- File        : MDCT.VHD
16 
-- Created     : Sat Feb 25 16:12 2006
17 
--
18 
--------------------------------------------------------------------------------
19 
--
20 
--  Description : Discrete Cosine Transform - chip top level (w/ memories)
21 
--
22 
--------------------------------------------------------------------------------
23 
 
24 
 
25 
library IEEE;
26 
  use IEEE.STD_LOGIC_1164.all;
27 
 
28 
library WORK;
29 
  use WORK.MDCT_PKG.all;
30 
 
31 
 
32 
entity MDCT is
33 
        port(
34 
                clk          : in STD_LOGIC;
35 
                rst          : in std_logic;
36 
    dcti         : in std_logic_vector(IP_W-1 downto 0);
37 
    idv          : in STD_LOGIC;
38 
 
39 
    ready        : out STD_LOGIC; -- ready for input data
40 
    odv          : out STD_LOGIC;
41 
    dcto         : out std_logic_vector(COE_W-1 downto 0);
42 
    -- debug
43 
    odv1         : out STD_LOGIC;
44 
    dcto1        : out std_logic_vector(OP_W-1 downto 0)
45 
 
46 
                );
47 
end MDCT;
48 
 
49 
architecture RTL of MDCT is
50 
 
51 
------------------------------
52 
-- 1D DCT
53 
------------------------------
54 
component DCT1D
55 
        port(
56 
                clk          : in STD_LOGIC;
57 
                rst          : in std_logic;
58 
      dcti         : in std_logic_vector(IP_W-1 downto 0);
59 
      idv          : in STD_LOGIC;
60 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
61 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
62 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
63 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
64 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
65 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
66 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
67 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
68 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
69 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
70 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
71 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
72 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
73 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
74 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
75 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
76 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
77 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
78 
      reqwrfail    : in STD_LOGIC;
79 
 
80 
      ready        : out STD_LOGIC; -- read from FIFO
81 
      odv          : out STD_LOGIC;
82 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
83 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
84 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
85 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
86 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
87 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
88 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
89 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
90 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
91 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
92 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
93 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
94 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
95 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
96 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
97 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
98 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
99 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
100 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
101 
      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
102 
      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
103 
      ramwe        : out STD_LOGIC;
104 
      requestwr    : out STD_LOGIC;
105 
      releasewr    : out STD_LOGIC
106 
                );
107 
end component;
108 
 
109 
------------------------------
110 
-- 1D DCT (2nd stage)
111 
------------------------------
112 
component DCT2D
113 
        port(
114 
      clk          : in STD_LOGIC;
115 
      rst          : in std_logic;
116 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
117 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
118 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
119 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
120 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
121 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
122 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
123 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
124 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
125 
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
126 
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
127 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
128 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
129 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
130 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
131 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
132 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
133 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
134 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
135 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
136 
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
137 
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
138 
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
139 
      reqrdfail    : in STD_LOGIC;
140 
      dataready    : in STD_LOGIC;
141 
 
142 
      odv          : out STD_LOGIC;
143 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
144 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
145 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
146 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
147 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
148 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
149 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
150 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
151 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
152 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
153 
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
154 
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
155 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
156 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
157 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
158 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
159 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
160 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
161 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
162 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
163 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
164 
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
165 
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
166 
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
167 
      requestrd    : out STD_LOGIC;
168 
      releaserd    : out STD_LOGIC
169 
);
170 
end component;
171 
 
172 
------------------------------
173 
-- RAM
174 
------------------------------
175 
component RAM
176 
  port (
177 
        d                 : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
178 
        waddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
179 
        raddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
180 
        we                : in  STD_LOGIC;
181 
        clk               : in  STD_LOGIC;
182 
 
183 
        q                 : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
184 
  );
185 
end component;
186 
 
187 
------------------------------
188 
-- ROME
189 
------------------------------
190 
component ROME
191 
  port(
192 11 mikel262 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
193 
       clk          : in STD_LOGIC;
194 2 mikel262 
 
195 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
196 
  );
197 
end component;
198 
 
199 
------------------------------
200 
-- ROMO
201 
------------------------------
202 
component ROMO
203 
  port(
204 11 mikel262 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
205 
       clk          : in STD_LOGIC;
206 2 mikel262 
 
207 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
208 
  );
209 
end component;
210 
 
211 
------------------------------
212 
-- DBUFCTL
213 
------------------------------
214 
component DBUFCTL is
215 
        port(
216 
                clk          : in STD_LOGIC;
217 
                rst          : in STD_LOGIC;
218 
    requestwr    : in STD_LOGIC;
219 
    requestrd    : in STD_LOGIC;
220 
    releasewr    : in STD_LOGIC;
221 
    releaserd    : in STD_LOGIC;
222 
 
223 
    memswitchwr  : out STD_LOGIC;
224 
    memswitchrd  : out STD_LOGIC;
225 
    reqwrfail    : out STD_LOGIC;
226 
    reqrdfail    : out STD_LOGIC;
227 
    dataready    : out STD_LOGIC
228 
);
229 
end component;
230 
 
231 
signal romedatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
232 
signal romedatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
233 
signal romedatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
234 
signal romedatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
235 
signal romedatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
236 
signal romedatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
237 
signal romedatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
238 
signal romedatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
239 
signal romedatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
240 
signal romodatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
241 
signal romodatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
242 
signal romodatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
243 
signal romodatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
244 
signal romodatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
245 
signal romodatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
246 
signal romodatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
247 
signal romodatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
248 
signal romodatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
249 
signal ramdatao_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
250 
signal romeaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
251 
signal romeaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
252 
signal romeaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
253 
signal romeaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
254 
signal romeaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
255 
signal romeaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
256 
signal romeaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
257 
signal romeaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
258 
signal romeaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
259 
signal romoaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
260 
signal romoaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
261 
signal romoaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
262 
signal romoaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
263 
signal romoaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
264 
signal romoaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
265 
signal romoaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
266 
signal romoaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
267 
signal romoaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
268 
signal ramraddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
269 
signal ramwaddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
270 
signal ramdatai_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
271 
signal ramwe_s              : STD_LOGIC;
272 
 
273 
signal rome2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
274 
signal rome2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
275 
signal rome2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
276 
signal rome2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
277 
signal rome2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
278 
signal rome2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
279 
signal rome2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
280 
signal rome2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
281 
signal rome2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
282 
signal rome2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
283 
signal rome2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
284 
signal romo2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
285 
signal romo2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
286 
signal romo2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
287 
signal romo2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
288 
signal romo2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
289 
signal romo2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
290 
signal romo2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
291 
signal romo2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
292 
signal romo2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
293 
signal romo2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
294 
signal romo2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
295 
signal rome2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
296 
signal rome2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
297 
signal rome2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
298 
signal rome2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
299 
signal rome2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
300 
signal rome2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
301 
signal rome2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
302 
signal rome2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
303 
signal rome2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
304 
signal rome2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
305 
signal rome2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
306 
signal romo2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
307 
signal romo2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
308 
signal romo2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
309 
signal romo2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
310 
signal romo2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
311 
signal romo2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
312 
signal romo2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
313 
signal romo2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
314 
signal romo2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
315 
signal romo2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
316 
signal romo2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
317 
signal odv2_s                : STD_LOGIC;
318 
signal dcto2_s               : STD_LOGIC_VECTOR(OP_W-1 downto 0);
319 
signal trigger2_s            : STD_LOGIC;
320 
signal trigger1_s            : STD_LOGIC;
321 
signal ramdatao1_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
322 
signal ramdatao2_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
323 
signal ramwe1_s              : STD_LOGIC;
324 
signal ramwe2_s              : STD_LOGIC;
325 
signal memswitchrd_s         : STD_LOGIC;
326 
signal memswitchwr_s         : STD_LOGIC;
327 
signal reqwrfail_s           : STD_LOGIC;
328 
signal reqrdfail_s           : STD_LOGIC;
329 
signal dataready_s           : STD_LOGIC;
330 
signal requestwr_s           : STD_LOGIC;
331 
signal releasewr_s           : STD_LOGIC;
332 
signal requestrd_s           : STD_LOGIC;
333 
signal releaserd_s           : STD_LOGIC;
334 
 
335 
begin
336 
 
337 
------------------------------
338 
-- 1D DCT port map
339 
------------------------------
340 
U_DCT1D : DCT1D
341 
  port map(
342 
      clk          => clk,
343 
      rst          => rst,
344 
      dcti         => dcti,
345 
      idv          => idv,
346 
      romedatao0   => romedatao0_s,
347 
      romedatao1   => romedatao1_s,
348 
      romedatao2   => romedatao2_s,
349 
      romedatao3   => romedatao3_s,
350 
      romedatao4   => romedatao4_s,
351 
      romedatao5   => romedatao5_s,
352 
      romedatao6   => romedatao6_s,
353 
      romedatao7   => romedatao7_s,
354 
      romedatao8   => romedatao8_s,
355 
      romodatao0   => romodatao0_s,
356 
      romodatao1   => romodatao1_s,
357 
      romodatao2   => romodatao2_s,
358 
      romodatao3   => romodatao3_s,
359 
      romodatao4   => romodatao4_s,
360 
      romodatao5   => romodatao5_s,
361 
      romodatao6   => romodatao6_s,
362 
      romodatao7   => romodatao7_s,
363 
      romodatao8   => romodatao8_s,
364 
      reqwrfail    => reqwrfail_s,
365 
 
366 
      ready        => ready,
367 
      odv          => odv1,
368 
      dcto         => dcto1,
369 
      romeaddro0   => romeaddro0_s,
370 
      romeaddro1   => romeaddro1_s,
371 
      romeaddro2   => romeaddro2_s,
372 
      romeaddro3   => romeaddro3_s,
373 
      romeaddro4   => romeaddro4_s,
374 
      romeaddro5   => romeaddro5_s,
375 
      romeaddro6   => romeaddro6_s,
376 
      romeaddro7   => romeaddro7_s,
377 
      romeaddro8   => romeaddro8_s,
378 
      romoaddro0   => romoaddro0_s,
379 
      romoaddro1   => romoaddro1_s,
380 
      romoaddro2   => romoaddro2_s,
381 
      romoaddro3   => romoaddro3_s,
382 
      romoaddro4   => romoaddro4_s,
383 
      romoaddro5   => romoaddro5_s,
384 
      romoaddro6   => romoaddro6_s,
385 
      romoaddro7   => romoaddro7_s,
386 
      romoaddro8   => romoaddro8_s,
387 
      ramwaddro    => ramwaddro_s,
388 
      ramdatai     => ramdatai_s,
389 
      ramwe        => ramwe_s,
390 
      requestwr    => requestwr_s,
391 
      releasewr    => releasewr_s
392 
                );
393 
 
394 
------------------------------
395 
-- 1D DCT port map
396 
------------------------------
397 
U_DCT2D : DCT2D
398 
  port map(
399 
      clk          => clk,
400 
      rst          => rst,
401 
      romedatao0   => rome2datao0_s,
402 
      romedatao1   => rome2datao1_s,
403 
      romedatao2   => rome2datao2_s,
404 
      romedatao3   => rome2datao3_s,
405 
      romedatao4   => rome2datao4_s,
406 
      romedatao5   => rome2datao5_s,
407 
      romedatao6   => rome2datao6_s,
408 
      romedatao7   => rome2datao7_s,
409 
      romedatao8   => rome2datao8_s,
410 
      romedatao9   => rome2datao9_s,
411 
      romedatao10  => rome2datao10_s,
412 
      romodatao0   => romo2datao0_s,
413 
      romodatao1   => romo2datao1_s,
414 
      romodatao2   => romo2datao2_s,
415 
      romodatao3   => romo2datao3_s,
416 
      romodatao4   => romo2datao4_s,
417 
      romodatao5   => romo2datao5_s,
418 
      romodatao6   => romo2datao6_s,
419 
      romodatao7   => romo2datao7_s,
420 
      romodatao8   => romo2datao8_s,
421 
      romodatao9   => romo2datao9_s,
422 
      romodatao10  => romo2datao10_s,
423 
      ramdatao     => ramdatao_s,
424 
      reqrdfail    => reqrdfail_s,
425 
      dataready    => dataready_s,
426 
 
427 
      odv          => odv,
428 
      dcto         => dcto,
429 
      romeaddro0   => rome2addro0_s,
430 
      romeaddro1   => rome2addro1_s,
431 
      romeaddro2   => rome2addro2_s,
432 
      romeaddro3   => rome2addro3_s,
433 
      romeaddro4   => rome2addro4_s,
434 
      romeaddro5   => rome2addro5_s,
435 
      romeaddro6   => rome2addro6_s,
436 
      romeaddro7   => rome2addro7_s,
437 
      romeaddro8   => rome2addro8_s,
438 
      romeaddro9   => rome2addro9_s,
439 
      romeaddro10  => rome2addro10_s,
440 
      romoaddro0   => romo2addro0_s,
441 
      romoaddro1   => romo2addro1_s,
442 
      romoaddro2   => romo2addro2_s,
443 
      romoaddro3   => romo2addro3_s,
444 
      romoaddro4   => romo2addro4_s,
445 
      romoaddro5   => romo2addro5_s,
446 
      romoaddro6   => romo2addro6_s,
447 
      romoaddro7   => romo2addro7_s,
448 
      romoaddro8   => romo2addro8_s,
449 
      romoaddro9   => romo2addro9_s,
450 
      romoaddro10  => romo2addro10_s,
451 
      ramraddro    => ramraddro_s,
452 
      requestrd    => requestrd_s,
453 
      releaserd    => releaserd_s
454 
                );
455 
 
456 
------------------------------
457 
-- RAM1 port map
458 
------------------------------
459 
U1_RAM : RAM
460 
  port map (
461 
        d          => ramdatai_s,
462 
        waddr      => ramwaddro_s,
463 
        raddr      => ramraddro_s,
464 
        we         => ramwe1_s,
465 
        clk        => clk,
466 
 
467 
        q          => ramdatao1_s
468 
  );
469 
 
470 
------------------------------
471 
-- RAM2 port map
472 
------------------------------
473 
U2_RAM : RAM
474 
  port map (
475 
        d          => ramdatai_s,
476 
        waddr      => ramwaddro_s,
477 
        raddr      => ramraddro_s,
478 
        we         => ramwe2_s,
479 
        clk        => clk,
480 
 
481 
        q          => ramdatao2_s
482 
  );
483 
 
484 
-- double buffer switch
485 
ramwe1_s     <= ramwe_s when memswitchwr_s = '0' else '0';
486 
ramwe2_s     <= ramwe_s when memswitchwr_s = '1' else '0';
487 
ramdatao_s   <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
488 
 
489 
------------------------------
490 
-- DBUFCTL
491 
------------------------------
492 
U_DBUFCTL : DBUFCTL
493 
        port map(
494 
                clk            => clk,
495 
                rst            => rst,
496 
    requestwr      => requestwr_s,
497 
    requestrd      => requestrd_s,
498 
    releasewr      => releasewr_s,
499 
    releaserd      => releaserd_s,
500 
 
501 
    memswitchwr    => memswitchwr_s,
502 
    memswitchrd    => memswitchrd_s,
503 
    reqwrfail      => reqwrfail_s,
504 
    reqrdfail      => reqrdfail_s,
505 
    dataready      => dataready_s
506 
                );
507 
 
508 
------------------------------
509 
-- ROME port map
510 
------------------------------
511 
U1_ROME0 : ROME
512 
  port map(
513 11 mikel262 
       addr        => romeaddro0_s,
514 
       clk         => clk,
515 2 mikel262 
 
516 
       datao       => romedatao0_s
517 
  );
518 
 
519 
------------------------------
520 
-- ROME port map
521 
------------------------------
522 
U1_ROME1 : ROME
523 
  port map(
524 
       addr        => romeaddro1_s,
525 11 mikel262 
       clk         => clk,
526 2 mikel262 
 
527 
       datao       => romedatao1_s
528 
  );
529 
 
530 
------------------------------
531 
-- ROME port map
532 
------------------------------
533 
U1_ROME2 : ROME
534 
  port map(
535 11 mikel262 
       addr        => romeaddro2_s,
536 
       clk         => clk,
537 2 mikel262 
 
538 
       datao       => romedatao2_s
539 
  );
540 
 
541 
------------------------------
542 
-- ROME port map
543 
------------------------------
544 
U1_ROME3 : ROME
545 
  port map(
546 11 mikel262 
       addr        => romeaddro3_s,
547 
       clk         => clk,
548 2 mikel262 
 
549 
       datao       => romedatao3_s
550 
  );
551 
------------------------------
552 
-- ROME port map
553 
------------------------------
554 
U1_ROME4 : ROME
555 
  port map(
556 11 mikel262 
       addr        => romeaddro4_s,
557 
       clk         => clk,
558 2 mikel262 
 
559 
       datao       => romedatao4_s
560 
  );
561 
------------------------------
562 
-- ROME port map
563 
------------------------------
564 
U1_ROME5 : ROME
565 
  port map(
566 11 mikel262 
       addr        => romeaddro5_s,
567 
       clk         => clk,
568 2 mikel262 
 
569 
       datao       => romedatao5_s
570 
  );
571 
------------------------------
572 
-- ROME port map
573 
------------------------------
574 
U1_ROME6 : ROME
575 
  port map(
576 11 mikel262 
       addr        => romeaddro6_s,
577 
       clk         => clk,
578 2 mikel262 
 
579 
       datao       => romedatao6_s
580 
  );
581 
------------------------------
582 
-- ROME port map
583 
------------------------------
584 
U1_ROME7 : ROME
585 
  port map(
586 11 mikel262 
       addr        => romeaddro7_s,
587 
       clk         => clk,
588 2 mikel262 
 
589 
       datao       => romedatao7_s
590 
  );
591 
------------------------------
592 
-- ROME port map
593 
------------------------------
594 
U1_ROME8 : ROME
595 
  port map(
596 11 mikel262 
       addr        => romeaddro8_s,
597 
       clk         => clk,
598 2 mikel262 
 
599 
       datao       => romedatao8_s
600 
  );
601 
 
602 
------------------------------
603 
-- ROMO port map
604 
------------------------------
605 
U1_ROMO0 : ROMO
606 
  port map(
607 11 mikel262 
       addr        => romoaddro0_s,
608 
       clk         => clk,
609 2 mikel262 
 
610 
       datao       => romodatao0_s
611 
  );
612 
------------------------------
613 
-- ROMO port map
614 
------------------------------
615 
U1_ROMO1 : ROMO
616 
  port map(
617 11 mikel262 
       addr        => romoaddro1_s,
618 
       clk         => clk,
619 2 mikel262 
 
620 
       datao       => romodatao1_s
621 
  );
622 
------------------------------
623 
-- ROMO port map
624 
------------------------------
625 
U1_ROMO2 : ROMO
626 
  port map(
627 11 mikel262 
       addr        => romoaddro2_s,
628 
       clk         => clk,
629 2 mikel262 
 
630 
       datao       => romodatao2_s
631 
  );
632 
------------------------------
633 
-- ROMO port map
634 
------------------------------
635 
U1_ROMO3 : ROMO
636 
  port map(
637 11 mikel262 
       addr        => romoaddro3_s,
638 
       clk         => clk,
639 2 mikel262 
 
640 
       datao       => romodatao3_s
641 
  );
642 
------------------------------
643 
-- ROMO port map
644 
------------------------------
645 
U1_ROMO4 : ROMO
646 
  port map(
647 
       addr        => romoaddro4_s,
648 11 mikel262 
       clk         => clk,
649 2 mikel262 
 
650 
       datao       => romodatao4_s
651 
  );
652 
------------------------------
653 
-- ROMO port map
654 
------------------------------
655 
U1_ROMO5 : ROMO
656 
  port map(
657 11 mikel262 
       addr        => romoaddro5_s,
658 
       clk         => clk,
659 2 mikel262 
 
660 
       datao       => romodatao5_s
661 
  );
662 
------------------------------
663 
-- ROMO port map
664 
------------------------------
665 
U1_ROMO6 : ROMO
666 
  port map(
667 11 mikel262 
       addr        => romoaddro6_s,
668 
       clk         => clk,
669 2 mikel262 
 
670 
       datao       => romodatao6_s
671 
  );
672 
------------------------------
673 
-- ROMO port map
674 
------------------------------
675 
U1_ROMO7 : ROMO
676 
  port map(
677 11 mikel262 
       addr        => romoaddro7_s,
678 
       clk         => clk,
679 2 mikel262 
 
680 
       datao       => romodatao7_s
681 
  );
682 
------------------------------
683 
-- ROMO port map
684 
------------------------------
685 
U1_ROMO8 : ROMO
686 
  port map(
687 11 mikel262 
       addr        => romoaddro8_s,
688 
       clk         => clk,
689 2 mikel262 
 
690 
       datao       => romodatao8_s
691 
  );
692 
 
693 
------------------------------
694 
-- 2 stage ROMs
695 
------------------------------
696 
------------------------------
697 
-- ROME port map
698 
------------------------------
699 
U2_ROME0 : ROME
700 
  port map(
701 11 mikel262 
       addr        => rome2addro0_s,
702 
       clk         => clk,
703 2 mikel262 
 
704 
       datao       => rome2datao0_s
705 
  );
706 
 
707 
------------------------------
708 
-- ROME port map
709 
------------------------------
710 
U2_ROME1 : ROME
711 
  port map(
712 11 mikel262 
       addr        => rome2addro1_s,
713 
       clk         => clk,
714 2 mikel262 
 
715 
       datao       => rome2datao1_s
716 
  );
717 
 
718 
------------------------------
719 
-- ROME port map
720 
------------------------------
721 
U2_ROME2 : ROME
722 
  port map(
723 11 mikel262 
       addr        => rome2addro2_s,
724 
       clk         => clk,
725 2 mikel262 
 
726 
       datao       => rome2datao2_s
727 
  );
728 
 
729 
------------------------------
730 
-- ROME port map
731 
------------------------------
732 
U2_ROME3 : ROME
733 
  port map(
734 11 mikel262 
       addr        => rome2addro3_s,
735 
       clk         => clk,
736 2 mikel262 
 
737 
       datao       => rome2datao3_s
738 
  );
739 
------------------------------
740 
-- ROME port map
741 
------------------------------
742 
U2_ROME4 : ROME
743 
  port map(
744 11 mikel262 
       addr        => rome2addro4_s,
745 
       clk         => clk,
746 2 mikel262 
 
747 
       datao       => rome2datao4_s
748 
  );
749 
------------------------------
750 
-- ROME port map
751 
------------------------------
752 
U2_ROME5 : ROME
753 
  port map(
754 11 mikel262 
       addr        => rome2addro5_s,
755 
       clk         => clk,
756 2 mikel262 
 
757 
       datao       => rome2datao5_s
758 
  );
759 
------------------------------
760 
-- ROME port map
761 
------------------------------
762 
U2_ROME6 : ROME
763 
  port map(
764 11 mikel262 
       addr        => rome2addro6_s,
765 
       clk         => clk,
766 2 mikel262 
 
767 
       datao       => rome2datao6_s
768 
  );
769 
------------------------------
770 
-- ROME port map
771 
------------------------------
772 
U2_ROME7 : ROME
773 
  port map(
774 11 mikel262 
       addr        => rome2addro7_s,
775 
       clk         => clk,
776 2 mikel262 
 
777 
       datao       => rome2datao7_s
778 
  );
779 
------------------------------
780 
-- ROME port map
781 
------------------------------
782 
U2_ROME8 : ROME
783 
  port map(
784 11 mikel262 
       addr        => rome2addro8_s,
785 
       clk         => clk,
786 2 mikel262 
 
787 
       datao       => rome2datao8_s
788 
  );
789 
------------------------------
790 
-- ROME port map
791 
------------------------------
792 
U2_ROME9 : ROME
793 
  port map(
794 11 mikel262 
       addr        => rome2addro9_s,
795 
       clk         => clk,
796 2 mikel262 
 
797 
       datao       => rome2datao9_s
798 
  );
799 
------------------------------
800 
-- ROME port map
801 
------------------------------
802 
U2_ROME10 : ROME
803 
  port map(
804 11 mikel262 
       addr        => rome2addro10_s,
805 
       clk         => clk,
806 2 mikel262 
 
807 
       datao       => rome2datao10_s
808 
  );
809 
 
810 
------------------------------
811 
-- ROMO port map
812 
------------------------------
813 
U2_ROMO0 : ROMO
814 
  port map(
815 11 mikel262 
       addr        => romo2addro0_s,
816 
       clk         => clk,
817 2 mikel262 
 
818 
       datao       => romo2datao0_s
819 
  );
820 
------------------------------
821 
-- ROMO port map
822 
------------------------------
823 
U2_ROMO1 : ROMO
824 
  port map(
825 11 mikel262 
       addr        => romo2addro1_s,
826 
       clk         => clk,
827 2 mikel262 
 
828 
       datao       => romo2datao1_s
829 
  );
830 
------------------------------
831 
-- ROMO port map
832 
------------------------------
833 
U2_ROMO2 : ROMO
834 
  port map(
835 11 mikel262 
       addr        => romo2addro2_s,
836 
       clk         => clk,
837 2 mikel262 
 
838 
       datao       => romo2datao2_s
839 
  );
840 
------------------------------
841 
-- ROMO port map
842 
------------------------------
843 
U2_ROMO3 : ROMO
844 
  port map(
845 11 mikel262 
       addr        => romo2addro3_s,
846 
       clk         => clk,
847 2 mikel262 
 
848 
       datao       => romo2datao3_s
849 
  );
850 
------------------------------
851 
-- ROMO port map
852 
------------------------------
853 
U2_ROMO4 : ROMO
854 
  port map(
855 11 mikel262 
       addr        => romo2addro4_s,
856 
       clk         => clk,
857 2 mikel262 
 
858 
       datao       => romo2datao4_s
859 
  );
860 
------------------------------
861 
-- ROMO port map
862 
------------------------------
863 
U2_ROMO5 : ROMO
864 
  port map(
865 11 mikel262 
       addr        => romo2addro5_s,
866 
       clk         => clk,
867 2 mikel262 
 
868 
       datao       => romo2datao5_s
869 
  );
870 
------------------------------
871 
-- ROMO port map
872 
------------------------------
873 
U2_ROMO6 : ROMO
874 
  port map(
875 11 mikel262 
       addr        => romo2addro6_s,
876 
       clk         => clk,
877 2 mikel262 
 
878 
       datao       => romo2datao6_s
879 
  );
880 
------------------------------
881 
-- ROMO port map
882 
------------------------------
883 
U2_ROMO7 : ROMO
884 
  port map(
885 11 mikel262 
       addr        => romo2addro7_s,
886 
       clk         => clk,
887 2 mikel262 
 
888 
       datao       => romo2datao7_s
889 
  );
890 
------------------------------
891 
-- ROMO port map
892 
------------------------------
893 
U2_ROMO8 : ROMO
894 
  port map(
895 11 mikel262 
       addr        => romo2addro8_s,
896 
       clk         => clk,
897 2 mikel262 
 
898 
       datao       => romo2datao8_s
899 
  );
900 
------------------------------
901 
-- ROMO port map
902 
------------------------------
903 
U2_ROMO9 : ROMO
904 
  port map(
905 11 mikel262 
       addr        => romo2addro9_s,
906 
       clk         => clk,
907 2 mikel262 
 
908 
       datao       => romo2datao9_s
909 
  );
910 
------------------------------
911 
-- ROMO port map
912 
------------------------------
913 
U2_ROMO10 : ROMO
914 
  port map(
915 11 mikel262 
       addr        => romo2addro10_s,
916 
       clk         => clk,
917 2 mikel262 
 
918 
       datao       => romo2datao10_s
919 
  );
920 
 
921 
end RTL;

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