OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] [mdct/] [trunk/] [source/] [MDCT.VHD] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : DCT
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
-- Company     : None
12 
--
13 
--------------------------------------------------------------------------------
14 
--
15 
-- File        : MDCT.VHD
16 
-- Created     : Sat Feb 25 16:12 2006
17 
--
18 
--------------------------------------------------------------------------------
19 
--
20 
--  Description : Discrete Cosine Transform - chip top level (w/ memories)
21 
--
22 
--------------------------------------------------------------------------------
23 
 
24 
 
25 
library IEEE;
26 
  use IEEE.STD_LOGIC_1164.all;
27 
 
28 
library WORK;
29 
  use WORK.MDCT_PKG.all;
30 
 
31 
 
32 
entity MDCT is
33 
        port(
34 
                clk          : in STD_LOGIC;
35 
                rst          : in std_logic;
36 
    dcti         : in std_logic_vector(IP_W-1 downto 0);
37 
    idv          : in STD_LOGIC;
38 
 
39 
    odv          : out STD_LOGIC;
40 
    dcto         : out std_logic_vector(COE_W-1 downto 0);
41 
    -- debug
42 
    odv1         : out STD_LOGIC;
43 
    dcto1        : out std_logic_vector(OP_W-1 downto 0)
44 
 
45 
                );
46 
end MDCT;
47 
 
48 
architecture RTL of MDCT is
49 
 
50 
------------------------------
51 
-- 1D DCT
52 
------------------------------
53 
component DCT1D
54 
        port(
55 15 mikel262 
                  clk          : in STD_LOGIC;
56 
                  rst          : in std_logic;
57 2 mikel262 
      dcti         : in std_logic_vector(IP_W-1 downto 0);
58 
      idv          : in STD_LOGIC;
59 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
60 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
61 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
62 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
63 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
64 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
65 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
66 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
67 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
68 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
69 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
70 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
71 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
72 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
73 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
74 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
75 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
76 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
77 
 
78 
      odv          : out STD_LOGIC;
79 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
80 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
81 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
82 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
83 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
84 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
85 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
86 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
87 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
88 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
89 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
90 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
91 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
92 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
93 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
94 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
95 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
96 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
97 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
98 
      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
99 
      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
100 
      ramwe        : out STD_LOGIC;
101 15 mikel262 
      wmemsel      : out STD_LOGIC
102 2 mikel262 
                );
103 
end component;
104 
 
105 
------------------------------
106 
-- 1D DCT (2nd stage)
107 
------------------------------
108 
component DCT2D
109 
        port(
110 
      clk          : in STD_LOGIC;
111 
      rst          : in std_logic;
112 
      romedatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
113 
      romedatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
114 
      romedatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
115 
      romedatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
116 
      romedatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
117 
      romedatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
118 
      romedatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
119 
      romedatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
120 
      romedatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
121 
      romedatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
122 
      romedatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
123 
      romodatao0   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
124 
      romodatao1   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
125 
      romodatao2   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
126 
      romodatao3   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
127 
      romodatao4   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
128 
      romodatao5   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
129 
      romodatao6   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
130 
      romodatao7   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
131 
      romodatao8   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
132 
      romodatao9   : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
133 
      romodatao10  : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
134 
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
135 
      dataready    : in STD_LOGIC;
136 
 
137 
      odv          : out STD_LOGIC;
138 
      dcto         : out std_logic_vector(OP_W-1 downto 0);
139 
      romeaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
140 
      romeaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
141 
      romeaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
142 
      romeaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
143 
      romeaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
144 
      romeaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
145 
      romeaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
146 
      romeaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
147 
      romeaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
148 
      romeaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
149 
      romeaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
150 
      romoaddro0   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
151 
      romoaddro1   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
152 
      romoaddro2   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
153 
      romoaddro3   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
154 
      romoaddro4   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
155 
      romoaddro5   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
156 
      romoaddro6   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
157 
      romoaddro7   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
158 
      romoaddro8   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
159 
      romoaddro9   : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
160 
      romoaddro10  : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
161 
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
162 15 mikel262 
      rmemsel      : out STD_LOGIC;
163 
      datareadyack : out STD_LOGIC
164 2 mikel262 
);
165 
end component;
166 
 
167 
------------------------------
168 
-- RAM
169 
------------------------------
170 
component RAM
171 
  port (
172 
        d                 : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
173 
        waddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
174 
        raddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
175 
        we                : in  STD_LOGIC;
176 
        clk               : in  STD_LOGIC;
177 
 
178 
        q                 : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
179 
  );
180 
end component;
181 
 
182 
------------------------------
183 
-- ROME
184 
------------------------------
185 
component ROME
186 
  port(
187 11 mikel262 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
188 
       clk          : in STD_LOGIC;
189 2 mikel262 
 
190 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
191 
  );
192 
end component;
193 
 
194 
------------------------------
195 
-- ROMO
196 
------------------------------
197 
component ROMO
198 
  port(
199 11 mikel262 
       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
200 
       clk          : in STD_LOGIC;
201 2 mikel262 
 
202 
       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
203 
  );
204 
end component;
205 
 
206 
------------------------------
207 
-- DBUFCTL
208 
------------------------------
209 18 mikel262 
component DBUFCTL
210 2 mikel262 
        port(
211 
                clk          : in STD_LOGIC;
212 
                rst          : in STD_LOGIC;
213 15 mikel262 
    wmemsel      : in STD_LOGIC;
214 
    rmemsel      : in STD_LOGIC;
215 
    datareadyack : in STD_LOGIC;
216 2 mikel262 
 
217 
    memswitchwr  : out STD_LOGIC;
218 
    memswitchrd  : out STD_LOGIC;
219 15 mikel262 
    dataready    : out STD_LOGIC
220 2 mikel262 
);
221 
end component;
222 
 
223 
signal romedatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
224 
signal romedatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
225 
signal romedatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
226 
signal romedatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
227 
signal romedatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
228 
signal romedatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
229 
signal romedatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
230 
signal romedatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
231 
signal romedatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
232 
signal romodatao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
233 
signal romodatao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
234 
signal romodatao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
235 
signal romodatao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
236 
signal romodatao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
237 
signal romodatao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
238 
signal romodatao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
239 
signal romodatao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
240 
signal romodatao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
241 
signal ramdatao_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
242 
signal romeaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
243 
signal romeaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
244 
signal romeaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
245 
signal romeaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
246 
signal romeaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
247 
signal romeaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
248 
signal romeaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
249 
signal romeaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
250 
signal romeaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
251 
signal romoaddro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
252 
signal romoaddro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
253 
signal romoaddro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
254 
signal romoaddro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
255 
signal romoaddro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
256 
signal romoaddro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
257 
signal romoaddro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
258 
signal romoaddro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
259 
signal romoaddro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
260 
signal ramraddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
261 
signal ramwaddro_s          : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
262 
signal ramdatai_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
263 
signal ramwe_s              : STD_LOGIC;
264 
 
265 
signal rome2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
266 
signal rome2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
267 
signal rome2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
268 
signal rome2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
269 
signal rome2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
270 
signal rome2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
271 
signal rome2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
272 
signal rome2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
273 
signal rome2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
274 
signal rome2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
275 
signal rome2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
276 
signal romo2datao0_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
277 
signal romo2datao1_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
278 
signal romo2datao2_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
279 
signal romo2datao3_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
280 
signal romo2datao4_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
281 
signal romo2datao5_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
282 
signal romo2datao6_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
283 
signal romo2datao7_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
284 
signal romo2datao8_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
285 
signal romo2datao9_s         : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
286 
signal romo2datao10_s        : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
287 
signal rome2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
288 
signal rome2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
289 
signal rome2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
290 
signal rome2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
291 
signal rome2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
292 
signal rome2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
293 
signal rome2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
294 
signal rome2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
295 
signal rome2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
296 
signal rome2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
297 
signal rome2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
298 
signal romo2addro0_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
299 
signal romo2addro1_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
300 
signal romo2addro2_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
301 
signal romo2addro3_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
302 
signal romo2addro4_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
303 
signal romo2addro5_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
304 
signal romo2addro6_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
305 
signal romo2addro7_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
306 
signal romo2addro8_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
307 
signal romo2addro9_s         : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
308 
signal romo2addro10_s        : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
309 
signal odv2_s                : STD_LOGIC;
310 
signal dcto2_s               : STD_LOGIC_VECTOR(OP_W-1 downto 0);
311 
signal trigger2_s            : STD_LOGIC;
312 
signal trigger1_s            : STD_LOGIC;
313 
signal ramdatao1_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
314 
signal ramdatao2_s           : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
315 
signal ramwe1_s              : STD_LOGIC;
316 
signal ramwe2_s              : STD_LOGIC;
317 
signal memswitchrd_s         : STD_LOGIC;
318 
signal memswitchwr_s         : STD_LOGIC;
319 15 mikel262 
signal wmemsel_s             : STD_LOGIC;
320 
signal rmemsel_s             : STD_LOGIC;
321 2 mikel262 
signal dataready_s           : STD_LOGIC;
322 15 mikel262 
signal datareadyack_s        : STD_LOGIC;
323 2 mikel262 
 
324 
begin
325 
 
326 
------------------------------
327 
-- 1D DCT port map
328 
------------------------------
329 
U_DCT1D : DCT1D
330 
  port map(
331 
      clk          => clk,
332 
      rst          => rst,
333 
      dcti         => dcti,
334 
      idv          => idv,
335 
      romedatao0   => romedatao0_s,
336 
      romedatao1   => romedatao1_s,
337 
      romedatao2   => romedatao2_s,
338 
      romedatao3   => romedatao3_s,
339 
      romedatao4   => romedatao4_s,
340 
      romedatao5   => romedatao5_s,
341 
      romedatao6   => romedatao6_s,
342 
      romedatao7   => romedatao7_s,
343 
      romedatao8   => romedatao8_s,
344 
      romodatao0   => romodatao0_s,
345 
      romodatao1   => romodatao1_s,
346 
      romodatao2   => romodatao2_s,
347 
      romodatao3   => romodatao3_s,
348 
      romodatao4   => romodatao4_s,
349 
      romodatao5   => romodatao5_s,
350 
      romodatao6   => romodatao6_s,
351 
      romodatao7   => romodatao7_s,
352 15 mikel262 
      romodatao8   => romodatao8_s,
353 
 
354 2 mikel262 
      odv          => odv1,
355 
      dcto         => dcto1,
356 
      romeaddro0   => romeaddro0_s,
357 
      romeaddro1   => romeaddro1_s,
358 
      romeaddro2   => romeaddro2_s,
359 
      romeaddro3   => romeaddro3_s,
360 
      romeaddro4   => romeaddro4_s,
361 
      romeaddro5   => romeaddro5_s,
362 
      romeaddro6   => romeaddro6_s,
363 
      romeaddro7   => romeaddro7_s,
364 
      romeaddro8   => romeaddro8_s,
365 
      romoaddro0   => romoaddro0_s,
366 
      romoaddro1   => romoaddro1_s,
367 
      romoaddro2   => romoaddro2_s,
368 
      romoaddro3   => romoaddro3_s,
369 
      romoaddro4   => romoaddro4_s,
370 
      romoaddro5   => romoaddro5_s,
371 
      romoaddro6   => romoaddro6_s,
372 
      romoaddro7   => romoaddro7_s,
373 
      romoaddro8   => romoaddro8_s,
374 
      ramwaddro    => ramwaddro_s,
375 
      ramdatai     => ramdatai_s,
376 
      ramwe        => ramwe_s,
377 15 mikel262 
      wmemsel      => wmemsel_s
378 2 mikel262 
                );
379 
 
380 
------------------------------
381 
-- 1D DCT port map
382 
------------------------------
383 
U_DCT2D : DCT2D
384 
  port map(
385 
      clk          => clk,
386 
      rst          => rst,
387 
      romedatao0   => rome2datao0_s,
388 
      romedatao1   => rome2datao1_s,
389 
      romedatao2   => rome2datao2_s,
390 
      romedatao3   => rome2datao3_s,
391 
      romedatao4   => rome2datao4_s,
392 
      romedatao5   => rome2datao5_s,
393 
      romedatao6   => rome2datao6_s,
394 
      romedatao7   => rome2datao7_s,
395 
      romedatao8   => rome2datao8_s,
396 
      romedatao9   => rome2datao9_s,
397 
      romedatao10  => rome2datao10_s,
398 
      romodatao0   => romo2datao0_s,
399 
      romodatao1   => romo2datao1_s,
400 
      romodatao2   => romo2datao2_s,
401 
      romodatao3   => romo2datao3_s,
402 
      romodatao4   => romo2datao4_s,
403 
      romodatao5   => romo2datao5_s,
404 
      romodatao6   => romo2datao6_s,
405 
      romodatao7   => romo2datao7_s,
406 
      romodatao8   => romo2datao8_s,
407 
      romodatao9   => romo2datao9_s,
408 
      romodatao10  => romo2datao10_s,
409 
      ramdatao     => ramdatao_s,
410 
      dataready    => dataready_s,
411 
 
412 
      odv          => odv,
413 
      dcto         => dcto,
414 
      romeaddro0   => rome2addro0_s,
415 
      romeaddro1   => rome2addro1_s,
416 
      romeaddro2   => rome2addro2_s,
417 
      romeaddro3   => rome2addro3_s,
418 
      romeaddro4   => rome2addro4_s,
419 
      romeaddro5   => rome2addro5_s,
420 
      romeaddro6   => rome2addro6_s,
421 
      romeaddro7   => rome2addro7_s,
422 
      romeaddro8   => rome2addro8_s,
423 
      romeaddro9   => rome2addro9_s,
424 
      romeaddro10  => rome2addro10_s,
425 
      romoaddro0   => romo2addro0_s,
426 
      romoaddro1   => romo2addro1_s,
427 
      romoaddro2   => romo2addro2_s,
428 
      romoaddro3   => romo2addro3_s,
429 
      romoaddro4   => romo2addro4_s,
430 
      romoaddro5   => romo2addro5_s,
431 
      romoaddro6   => romo2addro6_s,
432 
      romoaddro7   => romo2addro7_s,
433 
      romoaddro8   => romo2addro8_s,
434 
      romoaddro9   => romo2addro9_s,
435 
      romoaddro10  => romo2addro10_s,
436 
      ramraddro    => ramraddro_s,
437 15 mikel262 
      rmemsel      => rmemsel_s,
438 
      datareadyack => datareadyack_s
439 2 mikel262 
                );
440 
 
441 
------------------------------
442 
-- RAM1 port map
443 
------------------------------
444 
U1_RAM : RAM
445 
  port map (
446 
        d          => ramdatai_s,
447 
        waddr      => ramwaddro_s,
448 
        raddr      => ramraddro_s,
449 
        we         => ramwe1_s,
450 
        clk        => clk,
451 
 
452 
        q          => ramdatao1_s
453 
  );
454 
 
455 
------------------------------
456 
-- RAM2 port map
457 
------------------------------
458 
U2_RAM : RAM
459 
  port map (
460 
        d          => ramdatai_s,
461 
        waddr      => ramwaddro_s,
462 
        raddr      => ramraddro_s,
463 
        we         => ramwe2_s,
464 
        clk        => clk,
465 
 
466 
        q          => ramdatao2_s
467 
  );
468 
 
469 
-- double buffer switch
470 
ramwe1_s     <= ramwe_s when memswitchwr_s = '0' else '0';
471 
ramwe2_s     <= ramwe_s when memswitchwr_s = '1' else '0';
472 
ramdatao_s   <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
473 
 
474 
------------------------------
475 
-- DBUFCTL
476 
------------------------------
477 
U_DBUFCTL : DBUFCTL
478 
        port map(
479 
                clk            => clk,
480 
                rst            => rst,
481 15 mikel262 
    wmemsel        => wmemsel_s,
482 
    rmemsel        => rmemsel_s,
483 
    datareadyack   => datareadyack_s,
484 2 mikel262 
 
485 
    memswitchwr    => memswitchwr_s,
486 
    memswitchrd    => memswitchrd_s,
487 
    dataready      => dataready_s
488 
                );
489 
 
490 
------------------------------
491 
-- ROME port map
492 
------------------------------
493 
U1_ROME0 : ROME
494 
  port map(
495 11 mikel262 
       addr        => romeaddro0_s,
496 
       clk         => clk,
497 2 mikel262 
 
498 
       datao       => romedatao0_s
499 
  );
500 
 
501 
------------------------------
502 
-- ROME port map
503 
------------------------------
504 
U1_ROME1 : ROME
505 
  port map(
506 
       addr        => romeaddro1_s,
507 11 mikel262 
       clk         => clk,
508 2 mikel262 
 
509 
       datao       => romedatao1_s
510 
  );
511 
 
512 
------------------------------
513 
-- ROME port map
514 
------------------------------
515 
U1_ROME2 : ROME
516 
  port map(
517 11 mikel262 
       addr        => romeaddro2_s,
518 
       clk         => clk,
519 2 mikel262 
 
520 
       datao       => romedatao2_s
521 
  );
522 
 
523 
------------------------------
524 
-- ROME port map
525 
------------------------------
526 
U1_ROME3 : ROME
527 
  port map(
528 11 mikel262 
       addr        => romeaddro3_s,
529 
       clk         => clk,
530 2 mikel262 
 
531 
       datao       => romedatao3_s
532 
  );
533 
------------------------------
534 
-- ROME port map
535 
------------------------------
536 
U1_ROME4 : ROME
537 
  port map(
538 11 mikel262 
       addr        => romeaddro4_s,
539 
       clk         => clk,
540 2 mikel262 
 
541 
       datao       => romedatao4_s
542 
  );
543 
------------------------------
544 
-- ROME port map
545 
------------------------------
546 
U1_ROME5 : ROME
547 
  port map(
548 11 mikel262 
       addr        => romeaddro5_s,
549 
       clk         => clk,
550 2 mikel262 
 
551 
       datao       => romedatao5_s
552 
  );
553 
------------------------------
554 
-- ROME port map
555 
------------------------------
556 
U1_ROME6 : ROME
557 
  port map(
558 11 mikel262 
       addr        => romeaddro6_s,
559 
       clk         => clk,
560 2 mikel262 
 
561 
       datao       => romedatao6_s
562 
  );
563 
------------------------------
564 
-- ROME port map
565 
------------------------------
566 
U1_ROME7 : ROME
567 
  port map(
568 11 mikel262 
       addr        => romeaddro7_s,
569 
       clk         => clk,
570 2 mikel262 
 
571 
       datao       => romedatao7_s
572 
  );
573 
------------------------------
574 
-- ROME port map
575 
------------------------------
576 
U1_ROME8 : ROME
577 
  port map(
578 11 mikel262 
       addr        => romeaddro8_s,
579 
       clk         => clk,
580 2 mikel262 
 
581 
       datao       => romedatao8_s
582 
  );
583 
 
584 
------------------------------
585 
-- ROMO port map
586 
------------------------------
587 
U1_ROMO0 : ROMO
588 
  port map(
589 11 mikel262 
       addr        => romoaddro0_s,
590 
       clk         => clk,
591 2 mikel262 
 
592 
       datao       => romodatao0_s
593 
  );
594 
------------------------------
595 
-- ROMO port map
596 
------------------------------
597 
U1_ROMO1 : ROMO
598 
  port map(
599 11 mikel262 
       addr        => romoaddro1_s,
600 
       clk         => clk,
601 2 mikel262 
 
602 
       datao       => romodatao1_s
603 
  );
604 
------------------------------
605 
-- ROMO port map
606 
------------------------------
607 
U1_ROMO2 : ROMO
608 
  port map(
609 11 mikel262 
       addr        => romoaddro2_s,
610 
       clk         => clk,
611 2 mikel262 
 
612 
       datao       => romodatao2_s
613 
  );
614 
------------------------------
615 
-- ROMO port map
616 
------------------------------
617 
U1_ROMO3 : ROMO
618 
  port map(
619 11 mikel262 
       addr        => romoaddro3_s,
620 
       clk         => clk,
621 2 mikel262 
 
622 
       datao       => romodatao3_s
623 
  );
624 
------------------------------
625 
-- ROMO port map
626 
------------------------------
627 
U1_ROMO4 : ROMO
628 
  port map(
629 
       addr        => romoaddro4_s,
630 11 mikel262 
       clk         => clk,
631 2 mikel262 
 
632 
       datao       => romodatao4_s
633 
  );
634 
------------------------------
635 
-- ROMO port map
636 
------------------------------
637 
U1_ROMO5 : ROMO
638 
  port map(
639 11 mikel262 
       addr        => romoaddro5_s,
640 
       clk         => clk,
641 2 mikel262 
 
642 
       datao       => romodatao5_s
643 
  );
644 
------------------------------
645 
-- ROMO port map
646 
------------------------------
647 
U1_ROMO6 : ROMO
648 
  port map(
649 11 mikel262 
       addr        => romoaddro6_s,
650 
       clk         => clk,
651 2 mikel262 
 
652 
       datao       => romodatao6_s
653 
  );
654 
------------------------------
655 
-- ROMO port map
656 
------------------------------
657 
U1_ROMO7 : ROMO
658 
  port map(
659 11 mikel262 
       addr        => romoaddro7_s,
660 
       clk         => clk,
661 2 mikel262 
 
662 
       datao       => romodatao7_s
663 
  );
664 
------------------------------
665 
-- ROMO port map
666 
------------------------------
667 
U1_ROMO8 : ROMO
668 
  port map(
669 11 mikel262 
       addr        => romoaddro8_s,
670 
       clk         => clk,
671 2 mikel262 
 
672 
       datao       => romodatao8_s
673 
  );
674 
 
675 
------------------------------
676 
-- 2 stage ROMs
677 
------------------------------
678 
------------------------------
679 
-- ROME port map
680 
------------------------------
681 
U2_ROME0 : ROME
682 
  port map(
683 11 mikel262 
       addr        => rome2addro0_s,
684 
       clk         => clk,
685 2 mikel262 
 
686 
       datao       => rome2datao0_s
687 
  );
688 
 
689 
------------------------------
690 
-- ROME port map
691 
------------------------------
692 
U2_ROME1 : ROME
693 
  port map(
694 11 mikel262 
       addr        => rome2addro1_s,
695 
       clk         => clk,
696 2 mikel262 
 
697 
       datao       => rome2datao1_s
698 
  );
699 
 
700 
------------------------------
701 
-- ROME port map
702 
------------------------------
703 
U2_ROME2 : ROME
704 
  port map(
705 11 mikel262 
       addr        => rome2addro2_s,
706 
       clk         => clk,
707 2 mikel262 
 
708 
       datao       => rome2datao2_s
709 
  );
710 
 
711 
------------------------------
712 
-- ROME port map
713 
------------------------------
714 
U2_ROME3 : ROME
715 
  port map(
716 11 mikel262 
       addr        => rome2addro3_s,
717 
       clk         => clk,
718 2 mikel262 
 
719 
       datao       => rome2datao3_s
720 
  );
721 
------------------------------
722 
-- ROME port map
723 
------------------------------
724 
U2_ROME4 : ROME
725 
  port map(
726 11 mikel262 
       addr        => rome2addro4_s,
727 
       clk         => clk,
728 2 mikel262 
 
729 
       datao       => rome2datao4_s
730 
  );
731 
------------------------------
732 
-- ROME port map
733 
------------------------------
734 
U2_ROME5 : ROME
735 
  port map(
736 11 mikel262 
       addr        => rome2addro5_s,
737 
       clk         => clk,
738 2 mikel262 
 
739 
       datao       => rome2datao5_s
740 
  );
741 
------------------------------
742 
-- ROME port map
743 
------------------------------
744 
U2_ROME6 : ROME
745 
  port map(
746 11 mikel262 
       addr        => rome2addro6_s,
747 
       clk         => clk,
748 2 mikel262 
 
749 
       datao       => rome2datao6_s
750 
  );
751 
------------------------------
752 
-- ROME port map
753 
------------------------------
754 
U2_ROME7 : ROME
755 
  port map(
756 11 mikel262 
       addr        => rome2addro7_s,
757 
       clk         => clk,
758 2 mikel262 
 
759 
       datao       => rome2datao7_s
760 
  );
761 
------------------------------
762 
-- ROME port map
763 
------------------------------
764 
U2_ROME8 : ROME
765 
  port map(
766 11 mikel262 
       addr        => rome2addro8_s,
767 
       clk         => clk,
768 2 mikel262 
 
769 
       datao       => rome2datao8_s
770 
  );
771 
------------------------------
772 
-- ROME port map
773 
------------------------------
774 
U2_ROME9 : ROME
775 
  port map(
776 11 mikel262 
       addr        => rome2addro9_s,
777 
       clk         => clk,
778 2 mikel262 
 
779 
       datao       => rome2datao9_s
780 
  );
781 
------------------------------
782 
-- ROME port map
783 
------------------------------
784 
U2_ROME10 : ROME
785 
  port map(
786 11 mikel262 
       addr        => rome2addro10_s,
787 
       clk         => clk,
788 2 mikel262 
 
789 
       datao       => rome2datao10_s
790 
  );
791 
 
792 
------------------------------
793 
-- ROMO port map
794 
------------------------------
795 
U2_ROMO0 : ROMO
796 
  port map(
797 11 mikel262 
       addr        => romo2addro0_s,
798 
       clk         => clk,
799 2 mikel262 
 
800 
       datao       => romo2datao0_s
801 
  );
802 
------------------------------
803 
-- ROMO port map
804 
------------------------------
805 
U2_ROMO1 : ROMO
806 
  port map(
807 11 mikel262 
       addr        => romo2addro1_s,
808 
       clk         => clk,
809 2 mikel262 
 
810 
       datao       => romo2datao1_s
811 
  );
812 
------------------------------
813 
-- ROMO port map
814 
------------------------------
815 
U2_ROMO2 : ROMO
816 
  port map(
817 11 mikel262 
       addr        => romo2addro2_s,
818 
       clk         => clk,
819 2 mikel262 
 
820 
       datao       => romo2datao2_s
821 
  );
822 
------------------------------
823 
-- ROMO port map
824 
------------------------------
825 
U2_ROMO3 : ROMO
826 
  port map(
827 11 mikel262 
       addr        => romo2addro3_s,
828 
       clk         => clk,
829 2 mikel262 
 
830 
       datao       => romo2datao3_s
831 
  );
832 
------------------------------
833 
-- ROMO port map
834 
------------------------------
835 
U2_ROMO4 : ROMO
836 
  port map(
837 11 mikel262 
       addr        => romo2addro4_s,
838 
       clk         => clk,
839 2 mikel262 
 
840 
       datao       => romo2datao4_s
841 
  );
842 
------------------------------
843 
-- ROMO port map
844 
------------------------------
845 
U2_ROMO5 : ROMO
846 
  port map(
847 11 mikel262 
       addr        => romo2addro5_s,
848 
       clk         => clk,
849 2 mikel262 
 
850 
       datao       => romo2datao5_s
851 
  );
852 
------------------------------
853 
-- ROMO port map
854 
------------------------------
855 
U2_ROMO6 : ROMO
856 
  port map(
857 11 mikel262 
       addr        => romo2addro6_s,
858 
       clk         => clk,
859 2 mikel262 
 
860 
       datao       => romo2datao6_s
861 
  );
862 
------------------------------
863 
-- ROMO port map
864 
------------------------------
865 
U2_ROMO7 : ROMO
866 
  port map(
867 11 mikel262 
       addr        => romo2addro7_s,
868 
       clk         => clk,
869 2 mikel262 
 
870 
       datao       => romo2datao7_s
871 
  );
872 
------------------------------
873 
-- ROMO port map
874 
------------------------------
875 
U2_ROMO8 : ROMO
876 
  port map(
877 11 mikel262 
       addr        => romo2addro8_s,
878 
       clk         => clk,
879 2 mikel262 
 
880 
       datao       => romo2datao8_s
881 
  );
882 
------------------------------
883 
-- ROMO port map
884 
------------------------------
885 
U2_ROMO9 : ROMO
886 
  port map(
887 11 mikel262 
       addr        => romo2addro9_s,
888 
       clk         => clk,
889 2 mikel262 
 
890 
       datao       => romo2datao9_s
891 
  );
892 
------------------------------
893 
-- ROMO port map
894 
------------------------------
895 
U2_ROMO10 : ROMO
896 
  port map(
897 11 mikel262 
       addr        => romo2addro10_s,
898 
       clk         => clk,
899 2 mikel262 
 
900 
       datao       => romo2datao10_s
901 
  );
902 
 
903 
end RTL;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.