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[/] [mdct/] [trunk/] [source/] [ROME.VHD] - Blame information for rev 11

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--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--
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-- Title       : DCT
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-- Design      : MDCT Core
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-- Author      : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File        : ROME.VHD
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-- Created     : Sat Mar 5 7:37 2006
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--
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--------------------------------------------------------------------------------
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--
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--  Description : ROM for DCT matrix constant cosine coefficients (even part)
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--
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--------------------------------------------------------------------------------
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-- 5:0
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-- 5:4 = select matrix row (1 out of 4)
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-- 3:0 = select precomputed MAC ( 1 out of 16)
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library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use ieee.numeric_std.all;
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  use WORK.MDCT_PKG.all;
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entity ROME is
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  port(
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       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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       clk          : in  STD_LOGIC;
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       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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  );
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end ROME;
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architecture RTL of ROME is
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  type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
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            of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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  constant rom : ROM_TYPE :=
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    (
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    (others => '0'),
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     std_logic_vector( AP ),
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     std_logic_vector( AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP+AP+AP ),
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     std_logic_vector( AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP+AP+AP ),
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     std_logic_vector( AP+AP ),
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     std_logic_vector( AP+AP+AP ),
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     std_logic_vector( AP+AP+AP ),
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     std_logic_vector( AP+AP+AP+AP ),
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     (others => '0'),
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     std_logic_vector( BM ),
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     std_logic_vector( CM ),
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     std_logic_vector( CM+BM ),
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     std_logic_vector( CP ),
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     std_logic_vector( CP+BM ),
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     (others => '0'),
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     std_logic_vector( BM ),
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     std_logic_vector( BP ),
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     (others => '0'),
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     std_logic_vector( BP+CM ),
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     std_logic_vector( CM ),
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     std_logic_vector( BP+CP ),
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     std_logic_vector( CP ),
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     std_logic_vector( BP ),
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     (others => '0'),
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     (others => '0'),
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     std_logic_vector( AP ),
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     std_logic_vector( AM ),
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     (others => '0'),
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     std_logic_vector( AM ),
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     (others => '0'),
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     std_logic_vector( AM+AM ),
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     std_logic_vector( AM ),
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     std_logic_vector( AP ),
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     std_logic_vector( AP+AP ),
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     (others => '0'),
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     std_logic_vector( AP ),
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     (others => '0'),
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     std_logic_vector( AP ),
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     std_logic_vector( AM ),
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     (others => '0'),
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     (others => '0'),
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     std_logic_vector( CM ),
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     std_logic_vector( BP ),
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     std_logic_vector( BP+CM ),
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     std_logic_vector( BM ),
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     std_logic_vector( BM+CM ),
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     (others => '0'),
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     std_logic_vector( CM ),
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     std_logic_vector( CP ),
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     (others => '0'),
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     std_logic_vector( CP+BP ),
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     std_logic_vector( BP ),
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     std_logic_vector( CP+BM ),
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     std_logic_vector( BM ),
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     std_logic_vector( CP ),
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     (others => '0')
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     );
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  signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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  datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
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  process(clk)
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  begin
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   if clk = '1' and clk'event then
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     addr_reg <= addr;
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   end if;
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  end process;
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end RTL;
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--------------------------------------------------------------------------------
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