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-- --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2006 --
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-- --
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--------------------------------------------------------------------------------
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--
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-- Title : DCT
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-- Design : MDCT Core
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-- Author : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File : ROMO.VHD
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-- Created : Sat Mar 5 7:37 2006
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-- Modified : Dez. 30 2008 - Andreas Bergmann
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-- Libs and Typeconversion fixed due Xilinx Synthesis errors
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--
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--------------------------------------------------------------------------------
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--
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-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
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--
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--------------------------------------------------------------------------------
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-- 5:0
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-- 5:4 = select matrix row (1 out of 4)
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-- 3:0 = select precomputed MAC ( 1 out of 16)
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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-- use ieee.STD_LOGIC_signed.all;
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use IEEE.STD_LOGIC_arith.all;
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use WORK.MDCT_PKG.all;
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entity ROMO is
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port(
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addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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clk : in STD_LOGIC;
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datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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);
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end ROMO;
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architecture RTL of ROMO is
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type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
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of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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constant rom : ROM_TYPE :=
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(
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(others => '0'),
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conv_std_logic_vector( GP,ROMDATA_W ),
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conv_std_logic_vector( FP,ROMDATA_W ),
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conv_std_logic_vector( FP+GP,ROMDATA_W ),
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conv_std_logic_vector( EP,ROMDATA_W ),
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conv_std_logic_vector( EP+GP,ROMDATA_W ),
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conv_std_logic_vector( EP+FP,ROMDATA_W ),
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conv_std_logic_vector( EP+FP+GP,ROMDATA_W ),
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conv_std_logic_vector( DP,ROMDATA_W ),
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conv_std_logic_vector( DP+GP,ROMDATA_W ),
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conv_std_logic_vector( DP+FP,ROMDATA_W ),
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conv_std_logic_vector( DP+FP+GP,ROMDATA_W ),
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conv_std_logic_vector( DP+EP,ROMDATA_W ),
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conv_std_logic_vector( DP+EP+GP,ROMDATA_W ),
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conv_std_logic_vector( DP+EP+FP,ROMDATA_W ),
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conv_std_logic_vector( DP+EP+FP+GP,ROMDATA_W ),
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(others => '0'),
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conv_std_logic_vector( FM,ROMDATA_W ),
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conv_std_logic_vector( DM,ROMDATA_W ),
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conv_std_logic_vector( DM+FM,ROMDATA_W ),
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conv_std_logic_vector( GM,ROMDATA_W ),
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conv_std_logic_vector( GM+FM,ROMDATA_W ),
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conv_std_logic_vector( GM+DM,ROMDATA_W ),
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conv_std_logic_vector( GM+DM+FM,ROMDATA_W ),
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conv_std_logic_vector( EP,ROMDATA_W ),
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conv_std_logic_vector( EP+FM,ROMDATA_W ),
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conv_std_logic_vector( EP+DM,ROMDATA_W ),
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conv_std_logic_vector( EP+DM+FM,ROMDATA_W ),
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conv_std_logic_vector( EP+GM,ROMDATA_W ),
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conv_std_logic_vector( EP+GM+FM,ROMDATA_W ),
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conv_std_logic_vector( EP+GM+DM,ROMDATA_W ),
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conv_std_logic_vector( EP+GM+DM+FM,ROMDATA_W ),
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(others => '0'),
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conv_std_logic_vector( EP,ROMDATA_W ),
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conv_std_logic_vector( GP,ROMDATA_W ),
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conv_std_logic_vector( EP+GP,ROMDATA_W ),
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conv_std_logic_vector( DM,ROMDATA_W ),
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conv_std_logic_vector( DM+EP,ROMDATA_W ),
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conv_std_logic_vector( DM+GP,ROMDATA_W ),
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conv_std_logic_vector( DM+GP+EP,ROMDATA_W ),
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conv_std_logic_vector( FP,ROMDATA_W ),
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conv_std_logic_vector( FP+EP,ROMDATA_W ),
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conv_std_logic_vector( FP+GP,ROMDATA_W ),
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conv_std_logic_vector( FP+GP+EP,ROMDATA_W ),
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conv_std_logic_vector( FP+DM,ROMDATA_W ),
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conv_std_logic_vector( FP+DM+EP,ROMDATA_W ),
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conv_std_logic_vector( FP+DM+GP,ROMDATA_W ),
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conv_std_logic_vector( FP+DM+GP+EP,ROMDATA_W ),
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(others => '0'),
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conv_std_logic_vector( DM,ROMDATA_W ),
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conv_std_logic_vector( EP,ROMDATA_W ),
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conv_std_logic_vector( EP+DM,ROMDATA_W ),
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conv_std_logic_vector( FM,ROMDATA_W ),
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conv_std_logic_vector( FM+DM,ROMDATA_W ),
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conv_std_logic_vector( FM+EP,ROMDATA_W ),
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conv_std_logic_vector( FM+EP+DM,ROMDATA_W ),
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conv_std_logic_vector( GP,ROMDATA_W ),
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conv_std_logic_vector( GP+DM,ROMDATA_W ),
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conv_std_logic_vector( GP+EP,ROMDATA_W ),
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conv_std_logic_vector( GP+EP+DM,ROMDATA_W ),
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conv_std_logic_vector( GP+FM,ROMDATA_W ),
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conv_std_logic_vector( GP+FM+DM,ROMDATA_W ),
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conv_std_logic_vector( GP+FM+EP,ROMDATA_W ),
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conv_std_logic_vector( GP+FM+EP+DM,ROMDATA_W )
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);
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begin
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process(clk)
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begin
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if clk = '1' and clk'event then
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datao <= rom( CONV_INTEGER(UNSIGNED(addr)) );
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end if;
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end process;
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end RTL;
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