OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] [mdct/] [trunk/] [source/] [testbench/] [CLKGEN.VHD] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--
8 
-- Title       : CLKGEN
9 
-- Design      : MDCT Core
10 
-- Author      : Michal Krepa
11 
--
12 
--------------------------------------------------------------------------------
13 
--
14 
-- File        : CLKGEN.VHD
15 
-- Created     : Sat Mar 12 2006
16 
--
17 
--------------------------------------------------------------------------------
18 
--
19 
--  Description : Clock generator for simulation
20 
--
21 
--------------------------------------------------------------------------------
22 
library IEEE;
23 
  use IEEE.STD_LOGIC_1164.all;
24 
  use ieee.numeric_std.all;
25 
 
26 
library WORK;
27 18 mikel262 
  use WORK.MDCTTB_PKG.all;
28 2 mikel262 
 
29 
entity CLKGEN is
30 
  port (
31 
        clk               : out STD_LOGIC
32 
       );
33 
end CLKGEN;
34 
 
35 
--**************************************************************************--
36 
 
37 
architecture SIM of CLKGEN is
38 
 
39 
  signal clk_s            : STD_LOGIC;
40 
 
41 
begin
42 
 
43 
  ----------------------------------------------------------------------------
44 
  clk_gen_proc: -- clock generator
45 
  ----------------------------------------------------------------------------
46 
  process
47 
    constant PERIOD       : TIME := 1 us /(CLK_FREQ_C);
48 
  begin
49 
    clk_s                 <= '0';
50 
    wait for PERIOD/2;
51 
    clk_s                 <= '1';
52 
    wait for PERIOD/2;
53 
  end process;
54 
 
55 
  ----------------------------------------------------------------------------
56 
  clk_drv:
57 
  ----------------------------------------------------------------------------
58 
  clk                     <= clk_s;
59 
 
60 
end SIM;
61 
--**************************************************************************--

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.