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[/] [mdct/] [trunk/] [source/] [testbench/] [MDCT_TB.VHD] - Blame information for rev 27

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--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--
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-- Title       : MDCT_TB
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-- Design      : MDCT Core
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-- Author      : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File        : MDCT_TB.VHD
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-- Created     : Sat Mar 5 2006
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--
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--------------------------------------------------------------------------------
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--
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--  Description : Testbench top-level
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--
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--------------------------------------------------------------------------------
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library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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library WORK;
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  use WORK.MDCT_PKG.all;
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entity TB_MDCT is
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end TB_MDCT;
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--**************************************************************************--
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architecture TB of TB_MDCT is
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------------------------------
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-- MDCT
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------------------------------
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component MDCT
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        port(
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                clk          : in STD_LOGIC;
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                rst          : in std_logic;
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    dcti         : in std_logic_vector(IP_W-1 downto 0);
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    idv          : in STD_LOGIC;
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    odv          : out STD_LOGIC;
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                dcto         : out std_logic_vector(COE_W-1 downto 0);
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      -- debug
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    odv1         : out STD_LOGIC;
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    dcto1        : out std_logic_vector(OP_W-1 downto 0)
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                );
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end component;
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------------------------------
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-- Clock generator
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------------------------------
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component CLKGEN
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  port (
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        clk               : out STD_LOGIC
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       );
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end component;
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------------------------------
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-- Input image generator
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------------------------------
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component INPIMAGE
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  port (
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        clk               : in STD_LOGIC;
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        odv1              : in STD_LOGIC;
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        dcto1             : in STD_LOGIC_VECTOR(OP_W-1 downto 0);
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        odv               : in STD_LOGIC;
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        dcto              : in STD_LOGIC_VECTOR(COE_W-1 downto 0);
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        rst               : out STD_LOGIC;
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        imageo            : out STD_LOGIC_VECTOR(IP_W-1 downto 0);
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        dv                : out STD_LOGIC;
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        testend           : out BOOLEAN
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       );
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end component;
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signal clk_s               : STD_LOGIC;
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signal clk_gen_s           : STD_LOGIC;
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signal gate_clk_s          : STD_LOGIC;
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signal rst_s               : STD_LOGIC;
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signal dcti_s              : STD_LOGIC_VECTOR(IP_W-1 downto 0);
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signal idv_s               : STD_LOGIC;
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signal odv_s               : STD_LOGIC;
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signal dcto_s              : STD_LOGIC_VECTOR(COE_W-1 downto 0);
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signal odv1_s              : STD_LOGIC;
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signal dcto1_s             : STD_LOGIC_VECTOR(OP_W-1 downto 0);
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signal testend_s           : BOOLEAN;
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------------------------------
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-- architecture begin
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------------------------------
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begin
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------------------------------
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-- MDCT port map
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------------------------------
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U_MDCT : MDCT
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  port map(
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                  clk          => clk_s,
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                  rst          => rst_s,
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      dcti         => dcti_s,
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      idv          => idv_s,
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      odv          => odv_s,
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      dcto         => dcto_s,
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      odv1         => odv1_s,
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      dcto1        => dcto1_s
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                );
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------------------------------
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-- CLKGEN map
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------------------------------
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U_CLKGEN : CLKGEN
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  port map (
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        clk        => clk_gen_s
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       );
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------------------------------
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-- Input image generator
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------------------------------
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U_INPIMAGE : INPIMAGE
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  port map (
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        clk       => clk_s,
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        odv1      => odv1_s,
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        dcto1     => dcto1_s,
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        odv       => odv_s,
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        dcto      => dcto_s,
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        rst       => rst_s,
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        imageo    => dcti_s,
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        dv        => idv_s,
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        testend   => testend_s
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       );
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gate_clk_s <= '0' when testend_s = false else '1';
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clk_s <= clk_gen_s and (not gate_clk_s);
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end TB;
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-----------------------------------
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------------------------------
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-- configuration begin
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------------------------------
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configuration CONF_MDCT of TB_MDCT is
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  for TB
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    for U_MDCT : MDCT
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      use entity WORK.MDCT(RTL);
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    end for;
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    for U_INPIMAGE : INPIMAGE
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      use entity WORK.INPIMAGE(SIM);
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    end for;
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    for U_CLKGEN : CLKGEN
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      use entity WORK.CLKGEN(SIM);
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    end for;
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  end for;
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end CONF_MDCT;
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configuration CONF_MDCT_TIMING of TB_MDCT is
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  for TB
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    for U_MDCT : MDCT
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      use entity WORK.MDCT(STRUCTURE);
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    end for;
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    for U_INPIMAGE : INPIMAGE
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      use entity WORK.INPIMAGE(SIM);
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    end for;
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    for U_CLKGEN : CLKGEN
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      use entity WORK.CLKGEN(SIM);
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    end for;
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  end for;
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end CONF_MDCT_TIMING;
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--**************************************************************************--

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