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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [mc_defines.v] - Blame information for rev 28

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller Definitions                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_defines.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
//
//  $Date: 2002-03-06 15:10:34 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2001/12/12 06:35:15  rudi
//               *** empty log message ***
//
//               Revision 1.5  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.4  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.3  2001/09/10 13:44:17  rudi
//               *** empty log message ***
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.3  2001/06/12 15:19:49  rudi
//
//
//              Minor changes after running lint, and a small bug
//              fix reading csr and ba_mask registers.
//
//               Revision 1.2  2001/06/03 11:37:17  rudi
//
//
//               1) Fixed Chip Select Mask Register
//                      - Power On Value is now all ones
//                      - Comparison Logic is now correct
//
//               2) All resets are now asynchronous
//
//               3) Converted Power On Delay to an configurable item
//
//               4) Added reset to Chip Select Output Registers
//
//               5) Forcing all outputs to Hi-Z state during reset
//
//               Revision 1.1.1.1  2001/05/13 09:39:38  rudi
//               Created Directory Structure
//
//
//
//
 
`timescale 1ns / 10ps
 
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_REG_SEL              (wb_addr_i[31:29] == 3'b011)
 
// This define selects how the WISHBONE interface determines if
// the memory is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define MC_MEM_SEL              (wb_addr_i[31:29] == 3'h0)
 
/////////////////////////////////////////////////////////////////////
//
// This are the default Power-On Reset values for Chip Select
//
 
// This will be defined by the run script for my test bench ...
// Alternatively force here for synthesis ...
`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
 
// To run my default testbench default boot CS must be 3 !!!
`ifdef RUDIS_TB
`define MC_DEF_SEL              3'h3
`else
`define MC_DEF_SEL              3'h0
`endif
 
// Defines the default (reset) TMS value for the DEF_SEL chip select
`define MC_DEF_POR_TMS  32'hffff_ffff
 
 
/////////////////////////////////////////////////////////////////////
//
// Define how many Chip Selects to Implement
//
`define MC_HAVE_CS1     1
//`define MC_HAVE_CS2   1
//`define MC_HAVE_CS3   1
//`define MC_HAVE_CS4   1
//`define MC_HAVE_CS5   1
//`define MC_HAVE_CS6   1
//`define MC_HAVE_CS7   1
 
 
// To run my default testbench those need to there !!!
`ifdef RUDIS_TB
`define MC_HAVE_CS2     1
`define MC_HAVE_CS3     1
`define MC_HAVE_CS4     1
`define MC_HAVE_CS5     1
`endif
 
/////////////////////////////////////////////////////////////////////
//
// Init Refresh
//
// Number of Refresh Cycles to perform during SDRAM initialization.
// This varies between SDRAM manufacturer. Typically this value is
// between 2 and 8. This number must be smaller than 16.
`define MC_INIT_RFRC_CNT        2
 
/////////////////////////////////////////////////////////////////////
//
// Power On Delay
//
// Most if SDRAMs require some time to initialize before they can be used
// after power on. If the Memory Controller shall stall after power on to
// allow SDRAMs to finish the initialization process uncomment the below
// define statement
`define MC_POR_DELAY    1
 
// This value defines how many MEM_CLK cycles the Memory Controller should
// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250
// cycles.
`define MC_POR_DELAY_VAL        8'd250
 
 
// ===============================================================
// ===============================================================
// Various internal defines (DO NOT MODIFY !)
// ===============================================================
// ===============================================================
 
// Register settings encodings
`define MC_BW_8                 2'h0
`define MC_BW_16                2'h1
`define MC_BW_32                2'h2
 
`define MC_MEM_TYPE_SDRAM       3'h0
`define MC_MEM_TYPE_SRAM        3'h1
`define MC_MEM_TYPE_ACS         3'h2
`define MC_MEM_TYPE_SCS         3'h3
 
`define MC_MEM_SIZE_64          2'h0
`define MC_MEM_SIZE_128         2'h1
`define MC_MEM_SIZE_256         2'h2
 
// Command Valid, Ras_, Cas_, We_
`define MC_CMD_NOP              4'b0111
`define MC_CMD_PC               4'b1010
`define MC_CMD_ACT              4'b1011
`define MC_CMD_WR               4'b1100
`define MC_CMD_RD               4'b1101
`define MC_CMD_BT               4'b1110
`define MC_CMD_ARFR             4'b1001
`define MC_CMD_LMR              4'b1000
`define MC_CMD_XRD              4'b1111
`define MC_CMD_XWR              4'b1110
 
`define MC_SINGLE_BANK          1'b0
`define MC_ALL_BANKS            1'b1
 

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [mc_defines.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	25	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller Definitions ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: mc_defines.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $`
42			`//`
43			`// $Date: 2002-03-06 15:10:34 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.6 2001/12/12 06:35:15 rudi`
52			`// * empty log message *`
53			`//`
54			`// Revision 1.5 2001/12/11 02:47:19 rudi`
55			`//`
56			`// - Made some changes not to expect clock during reset ...`
57			`//`
58			`// Revision 1.4 2001/11/29 02:16:28 rudi`
59			`//`
60			`//`
61			`// - More Synthesis cleanup, mostly for speed`
62			`// - Several bug fixes`
63			`// - Changed code to avoid auto-precharge and`
64			`// burst-terminate combinations (apparently illegal ?)`
65			`// Now we will do a manual precharge ...`
66			`//`
67			`// Revision 1.3 2001/09/10 13:44:17 rudi`
68			`// * empty log message *`
69			`//`
70			`// Revision 1.2 2001/08/10 08:16:21 rudi`
71			`//`
72			`// - Changed IO names to be more clear.`
73			`// - Uniquifyed define names to be core specific.`
74			`// - Removed "Refresh Early" configuration`
75			`//`
76			`// Revision 1.1 2001/07/29 07:34:41 rudi`
77			`//`
78			`//`
79			`// 1) Changed Directory Structure`
80			`// 2) Fixed several minor bugs`
81			`//`
82			`// Revision 1.3 2001/06/12 15:19:49 rudi`
83			`//`
84			`//`
85			`// Minor changes after running lint, and a small bug`
86			`// fix reading csr and ba_mask registers.`
87			`//`
88			`// Revision 1.2 2001/06/03 11:37:17 rudi`
89			`//`
90			`//`
91			`// 1) Fixed Chip Select Mask Register`
92			`// - Power On Value is now all ones`
93			`// - Comparison Logic is now correct`
94			`//`
95			`// 2) All resets are now asynchronous`
96			`//`
97			`// 3) Converted Power On Delay to an configurable item`
98			`//`
99			`// 4) Added reset to Chip Select Output Registers`
100			`//`
101			`// 5) Forcing all outputs to Hi-Z state during reset`
102			`//`
103			`// Revision 1.1.1.1 2001/05/13 09:39:38 rudi`
104			`// Created Directory Structure`
105			`//`
106			`//`
107			`//`
108			`//`
109
110			`timescale 1ns / 10ps
111
112			`/////////////////////////////////////////////////////////////////////`
113			`//`
114			`// This define selects how the WISHBONE interface determines if`
115			`// the internal register file is selected.`
116			`// This should be a simple address decoder. "wb_addr_i" is the`
117			`// WISHBONE address bus (32 bits wide).`
118			`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011)
119
120			`// This define selects how the WISHBONE interface determines if`
121			`// the memory is selected.`
122			`// This should be a simple address decoder. "wb_addr_i" is the`
123			`// WISHBONE address bus (32 bits wide).`
124			`define MC_MEM_SEL (wb_addr_i[31:29] == 3'h0)
125
126			`/////////////////////////////////////////////////////////////////////`
127			`//`
128			`// This are the default Power-On Reset values for Chip Select`
129			`//`
130
131			`// This will be defined by the run script for my test bench ...`
132			`// Alternatively force here for synthesis ...`
133			`define RUDIS_TB 1
134
135			`// Defines which chip select is used for Power On booting`
136
137			`// To run my default testbench default boot CS must be 3 !!!`
138			`ifdef RUDIS_TB
139			`define MC_DEF_SEL 3'h3
140			`else
141			`define MC_DEF_SEL 3'h0
142			`endif
143
144			`// Defines the default (reset) TMS value for the DEF_SEL chip select`
145			`define MC_DEF_POR_TMS 32'hffff_ffff
146
147
148			`/////////////////////////////////////////////////////////////////////`
149			`//`
150			`// Define how many Chip Selects to Implement`
151			`//`
152			`define MC_HAVE_CS1 1
153			//`define MC_HAVE_CS2 1
154			//`define MC_HAVE_CS3 1
155			//`define MC_HAVE_CS4 1
156			//`define MC_HAVE_CS5 1
157			//`define MC_HAVE_CS6 1
158			//`define MC_HAVE_CS7 1
159
160
161			`// To run my default testbench those need to there !!!`
162			`ifdef RUDIS_TB
163			`define MC_HAVE_CS2 1
164			`define MC_HAVE_CS3 1
165			`define MC_HAVE_CS4 1
166			`define MC_HAVE_CS5 1
167			`endif
168
169			`/////////////////////////////////////////////////////////////////////`
170			`//`
171			`// Init Refresh`
172			`//`
173			`// Number of Refresh Cycles to perform during SDRAM initialization.`
174			`// This varies between SDRAM manufacturer. Typically this value is`
175			`// between 2 and 8. This number must be smaller than 16.`
176			`define MC_INIT_RFRC_CNT 2
177
178			`/////////////////////////////////////////////////////////////////////`
179			`//`
180			`// Power On Delay`
181			`//`
182			`// Most if SDRAMs require some time to initialize before they can be used`
183			`// after power on. If the Memory Controller shall stall after power on to`
184			`// allow SDRAMs to finish the initialization process uncomment the below`
185			`// define statement`
186			`define MC_POR_DELAY 1
187
188			`// This value defines how many MEM_CLK cycles the Memory Controller should`
189			`// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250`
190			`// cycles.`
191			`define MC_POR_DELAY_VAL 8'd250
192
193
194			`// ===============================================================`
195			`// ===============================================================`
196			`// Various internal defines (DO NOT MODIFY !)`
197			`// ===============================================================`
198			`// ===============================================================`
199
200			`// Register settings encodings`
201			`define MC_BW_8 2'h0
202			`define MC_BW_16 2'h1
203			`define MC_BW_32 2'h2
204
205			`define MC_MEM_TYPE_SDRAM 3'h0
206			`define MC_MEM_TYPE_SRAM 3'h1
207			`define MC_MEM_TYPE_ACS 3'h2
208			`define MC_MEM_TYPE_SCS 3'h3
209
210			`define MC_MEM_SIZE_64 2'h0
211			`define MC_MEM_SIZE_128 2'h1
212			`define MC_MEM_SIZE_256 2'h2
213
214			`// Command Valid, Ras_, Cas_, We_`
215			`define MC_CMD_NOP 4'b0111
216			`define MC_CMD_PC 4'b1010
217			`define MC_CMD_ACT 4'b1011
218			`define MC_CMD_WR 4'b1100
219			`define MC_CMD_RD 4'b1101
220			`define MC_CMD_BT 4'b1110
221			`define MC_CMD_ARFR 4'b1001
222			`define MC_CMD_LMR 4'b1000
223			`define MC_CMD_XRD 4'b1111
224			`define MC_CMD_XWR 4'b1110
225
226			`define MC_SINGLE_BANK 1'b0
227			`define MC_ALL_BANKS 1'b1
228