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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [mc_defines.v] - Blame information for rev 28

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1 25 rherveille
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE Memory Controller Definitions                     ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: mc_defines.v,v 1.1 2002-03-06 15:10:34 rherveille Exp $
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//
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//  $Date: 2002-03-06 15:10:34 $
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//  $Revision: 1.1 $
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//  $Author: rherveille $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.6  2001/12/12 06:35:15  rudi
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//               *** empty log message ***
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//
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//               Revision 1.5  2001/12/11 02:47:19  rudi
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//
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//               - Made some changes not to expect clock during reset ...
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//
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//               Revision 1.4  2001/11/29 02:16:28  rudi
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//
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//
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//               - More Synthesis cleanup, mostly for speed
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//               - Several bug fixes
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//               - Changed code to avoid auto-precharge and
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//                 burst-terminate combinations (apparently illegal ?)
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//                 Now we will do a manual precharge ...
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//
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//               Revision 1.3  2001/09/10 13:44:17  rudi
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//               *** empty log message ***
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//
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//               Revision 1.2  2001/08/10 08:16:21  rudi
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//
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//               - Changed IO names to be more clear.
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//               - Uniquifyed define names to be core specific.
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//               - Removed "Refresh Early" configuration
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//
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//               Revision 1.1  2001/07/29 07:34:41  rudi
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//
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//
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//               1) Changed Directory Structure
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//               2) Fixed several minor bugs
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//
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//               Revision 1.3  2001/06/12 15:19:49  rudi
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//
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//
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//              Minor changes after running lint, and a small bug
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//              fix reading csr and ba_mask registers.
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//
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//               Revision 1.2  2001/06/03 11:37:17  rudi
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//
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//
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//               1) Fixed Chip Select Mask Register
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//                      - Power On Value is now all ones
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//                      - Comparison Logic is now correct
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//
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//               2) All resets are now asynchronous
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//
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//               3) Converted Power On Delay to an configurable item
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//
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//               4) Added reset to Chip Select Output Registers
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//
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//               5) Forcing all outputs to Hi-Z state during reset
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//
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//               Revision 1.1.1.1  2001/05/13 09:39:38  rudi
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//               Created Directory Structure
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//
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//
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//
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//
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`timescale 1ns / 10ps
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/////////////////////////////////////////////////////////////////////
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//
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// This define selects how the WISHBONE interface determines if
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// the internal register file is selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// WISHBONE address bus (32 bits wide).
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`define MC_REG_SEL              (wb_addr_i[31:29] == 3'b011)
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// This define selects how the WISHBONE interface determines if
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// the memory is selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// WISHBONE address bus (32 bits wide).
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`define MC_MEM_SEL              (wb_addr_i[31:29] == 3'h0)
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/////////////////////////////////////////////////////////////////////
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//
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// This are the default Power-On Reset values for Chip Select
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//
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// This will be defined by the run script for my test bench ...
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// Alternatively force here for synthesis ...
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`define RUDIS_TB 1
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// Defines which chip select is used for Power On booting
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// To run my default testbench default boot CS must be 3 !!!
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`ifdef RUDIS_TB
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`define MC_DEF_SEL              3'h3
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`else
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`define MC_DEF_SEL              3'h0
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`endif
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// Defines the default (reset) TMS value for the DEF_SEL chip select
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`define MC_DEF_POR_TMS  32'hffff_ffff
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/////////////////////////////////////////////////////////////////////
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//
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// Define how many Chip Selects to Implement
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//
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`define MC_HAVE_CS1     1
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//`define MC_HAVE_CS2   1
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//`define MC_HAVE_CS3   1
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//`define MC_HAVE_CS4   1
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//`define MC_HAVE_CS5   1
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//`define MC_HAVE_CS6   1
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//`define MC_HAVE_CS7   1
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// To run my default testbench those need to there !!!
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`ifdef RUDIS_TB
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`define MC_HAVE_CS2     1
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`define MC_HAVE_CS3     1
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`define MC_HAVE_CS4     1
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`define MC_HAVE_CS5     1
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`endif
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/////////////////////////////////////////////////////////////////////
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//
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// Init Refresh
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//
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// Number of Refresh Cycles to perform during SDRAM initialization.
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// This varies between SDRAM manufacturer. Typically this value is
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// between 2 and 8. This number must be smaller than 16.
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`define MC_INIT_RFRC_CNT        2
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/////////////////////////////////////////////////////////////////////
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//
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// Power On Delay
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//
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// Most if SDRAMs require some time to initialize before they can be used
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// after power on. If the Memory Controller shall stall after power on to
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// allow SDRAMs to finish the initialization process uncomment the below
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// define statement
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`define MC_POR_DELAY    1
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// This value defines how many MEM_CLK cycles the Memory Controller should
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// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250
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// cycles.
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`define MC_POR_DELAY_VAL        8'd250
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// ===============================================================
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// ===============================================================
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// Various internal defines (DO NOT MODIFY !)
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// ===============================================================
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// ===============================================================
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// Register settings encodings
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`define MC_BW_8                 2'h0
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`define MC_BW_16                2'h1
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`define MC_BW_32                2'h2
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`define MC_MEM_TYPE_SDRAM       3'h0
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`define MC_MEM_TYPE_SRAM        3'h1
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`define MC_MEM_TYPE_ACS         3'h2
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`define MC_MEM_TYPE_SCS         3'h3
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`define MC_MEM_SIZE_64          2'h0
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`define MC_MEM_SIZE_128         2'h1
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`define MC_MEM_SIZE_256         2'h2
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// Command Valid, Ras_, Cas_, We_
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`define MC_CMD_NOP              4'b0111
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`define MC_CMD_PC               4'b1010
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`define MC_CMD_ACT              4'b1011
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`define MC_CMD_WR               4'b1100
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`define MC_CMD_RD               4'b1101
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`define MC_CMD_BT               4'b1110
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`define MC_CMD_ARFR             4'b1001
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`define MC_CMD_LMR              4'b1000
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`define MC_CMD_XRD              4'b1111
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`define MC_CMD_XWR              4'b1110
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`define MC_SINGLE_BANK          1'b0
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`define MC_ALL_BANKS            1'b1
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