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[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [models/] [m8kx8.v] - Blame information for rev 28

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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  CY7C185 model (Cypress 8kx8 fast asynchronous sram)          ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2002 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: m8kx8.v,v 1.1 2002-03-06 15:15:35 rherveille Exp $
//
//  $Date: 2002-03-06 15:15:35 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
//
 
`timescale 1ns/10ps
 
module A8Kx8(Address, dataIO, OEn, CE1n, CE2, WEn);
 
        //
        // parameters
        //
 
        //
        // inputs & outputs
        //
        input [12:0] Address;
        inout [ 7:0] dataIO;
        input        OEn;
        input        CE1n;
        input        CE2;
        input        WEn;
 
        //
        // variables
        //
        reg [ 7:0] mem_array  [8191:0];
 
        reg delayed_WE;
        reg [ 7:0] data_temp, dataIO1;
        reg is_write;
 
        wire CE = !CE1n && CE2;
        reg OE_OEn, OE_CE;
        wire OE = OE_OEn && OE_CE;
 
        reg read_cycle1, read_cycle2;
 
        time Trc;
        time Taa;
        time Toha;
        time Tace;
        time Tdoe;
        time Tlzoe;
        time Thzoe;
        time Tlzce;
        time Thzce;
 
        time Twc;
        time Tsce;
        time Taw;
        time Tpwe;
        time Tsd;
        time Thzwe;
        time Tlzwe;
 
        time CE_start, CE_end;
        time write_WE_start, read_WE_start;
        time dataIO_start;
        time Address_start;
        time OEn_start,  OEn_end;
 
        initial
                begin
                        read_cycle1 = 1'b0;
                        read_cycle2 = 1'b0;
 
                        // read cycle
                        Trc   = 20;
                        Taa   = 20;
                        Toha  = 5;
                        Tace  = 20;
                        Tdoe  = 9;
                        Tlzoe = 3;
                        Thzoe = 8;
                        Tlzce = 5; // not completely accurate. Tlzce2 = 3ns
                        Thzce = 8;
 
                        // write cycle
                        Twc   = 20;
                        Tsce  = 15;
                        Taw   = 15;
                        Tpwe  = 15;
                        Tsd   = 10;
                        Thzwe = 7;
                        Tlzwe = 5;
                end
 
        //
        // module body
        //
 
        // assign output
        assign dataIO = (OE && !delayed_WE) ? data_temp : 8'bz;
 
        // assign times
 
        always@(posedge CE)
                begin
                        CE_start <= $time;
 
                        #Tlzce OE_CE <= CE;
                end
 
        always@(negedge CE)
                begin
                        CE_end <= $time;
 
                        #Thzce OE_CE <= CE;
                end
 
        always@(dataIO)
                begin
                        dataIO_start <= $time;
                end
 
        always@(negedge WEn)
                begin
                        write_WE_start <= $time;
 
                        # Thzwe delayed_WE <= !WEn;
                end
 
        always@(posedge WEn)
                begin
                        read_WE_start <= $time;
 
                        #Tlzwe delayed_WE <= !WEn;
                end
 
        always@(Address)
                begin
                        Address_start <= $time;
                end
 
        always@(negedge OEn)
                begin
                        OEn_start <= $time;
 
                        #Tlzoe OE_OEn <= !OEn;
                end
 
        always@(posedge OEn)
                begin
                        OEn_end <= $time;
 
                        #Thzoe OE_OEn <= !OEn;
                end
        //
        // write cycles
        //
 
        always@(WEn or CE)
                is_write <= !WEn && CE;
 
        // write cycle no.1 & no.3 WE controlled
        always@(posedge WEn or negedge CE)
                begin
                        // check if CE asserted ( CE1n == 1'b0 && CE2 == 1'b1)
                        if (is_write)
                        begin
 
                                // check WE valid time
                                if ( ($time - write_WE_start) >= Tpwe)
                                begin
 
                                        // check CE valid time
                                        if ( ($time - CE_start) >= Tsce)
                                        begin
 
                                                // check data_in setup-time
                                                if ( ($time - dataIO_start) >= Tsd)
                                                begin
 
                                                        // check address valid time
                                                        if ( ($time - Address_start >= Taw) )
                                                                mem_array[Address] <= dataIO;
                                                        else
                                                                $display("Address setup to WE write end violation at time %t", $time);
                                                end
                                                else
                                                        $display("Data setup to WE write end violation at time %t", $time);
                                        end
                                        else
                                                $display("CE to WE write end violation at time %t", $time);
                                end
                                else
                                        $display("WE pulse width violation at time %t", $time);
                        end
                end
 
 
        //
        // Read cycles
        //
 
        always@(Address or WEn or CE or OEn)
                begin
                        // check if valid read cycle
                        if (CE && WEn)
                                begin
                                        if ( (($time - CE_start) >= Trc) && (CE_start >= CE_end) &&
                                                        (($time - OEn_start) >= Trc) && (OEn_start >= OEn_end) ) // ???
                                                begin
 
                                                        // check Trc
                                                        if ( ($time - Address_start < Trc) )
                                                        begin
                                                                $display("Read cycle time violation, caused by address change at time %t", $time);
                                                                $display("CE: %t, OEn: %t, Adr: %t", $time - CE_start, $time - OEn_start, $time - Address_start);
                                                        end
 
                                                        // read cycle no.1
                                                        read_cycle1 <= 1'b1;
                                                        read_cycle2 <= 1'b0;
                                                end
                                        else
                                                begin
                                                        // read cycle no.2
                                                        read_cycle1 <= 1'b0;
                                                        read_cycle2 <= 1'b1;
                                                end
                                end
                        else
                                begin
                                        read_cycle1 = 1'b0;
                                        read_cycle2 = 1'b0;
                                end
                end
 
 
        // perform actual read
        always
                begin
                        #1;
                        if (read_cycle1)
                                if ( ($time - Address_start) >= Taa)
                                        data_temp <= mem_array[Address];
                                else if ( ($time - Address_start >= Toha) )
                                        data_temp <= 8'bx;
 
                        if (read_cycle2)
                                if ( (($time - OEn_start) >= Tdoe) && (($time - CE_start) >= Tace) )
                                        data_temp <= mem_array[Address];
                                else if ( (($time - OEn_start) >= Tlzoe) && (($time - CE_start) >= Tlzce) )
                                        data_temp <= 8'bx;
                end
 
endmodule
 
 
 

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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [richard/] [verilog/] [models/] [m8kx8.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	26	rherveille	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// CY7C185 model (Cypress 8kx8 fast asynchronous sram) ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2002 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: m8kx8.v,v 1.1 2002-03-06 15:15:35 rherveille Exp $`
41			`//`
42			`// $Date: 2002-03-06 15:15:35 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`//`
49
50			`timescale 1ns/10ps
51
52			`module A8Kx8(Address, dataIO, OEn, CE1n, CE2, WEn);`
53
54			`//`
55			`// parameters`
56			`//`
57
58			`//`
59			`// inputs & outputs`
60			`//`
61			`input [12:0] Address;`
62			`inout [ 7:0] dataIO;`
63			`input OEn;`
64			`input CE1n;`
65			`input CE2;`
66			`input WEn;`
67
68			`//`
69			`// variables`
70			`//`
71			`reg [ 7:0] mem_array [8191:0];`
72
73			`reg delayed_WE;`
74			`reg [ 7:0] data_temp, dataIO1;`
75			`reg is_write;`
76
77			`wire CE = !CE1n && CE2;`
78			`reg OE_OEn, OE_CE;`
79			`wire OE = OE_OEn && OE_CE;`
80
81			`reg read_cycle1, read_cycle2;`
82
83			`time Trc;`
84			`time Taa;`
85			`time Toha;`
86			`time Tace;`
87			`time Tdoe;`
88			`time Tlzoe;`
89			`time Thzoe;`
90			`time Tlzce;`
91			`time Thzce;`
92
93			`time Twc;`
94			`time Tsce;`
95			`time Taw;`
96			`time Tpwe;`
97			`time Tsd;`
98			`time Thzwe;`
99			`time Tlzwe;`
100
101			`time CE_start, CE_end;`
102			`time write_WE_start, read_WE_start;`
103			`time dataIO_start;`
104			`time Address_start;`
105			`time OEn_start, OEn_end;`
106
107			`initial`
108			`begin`
109			`read_cycle1 = 1'b0;`
110			`read_cycle2 = 1'b0;`
111
112			`// read cycle`
113			`Trc = 20;`
114			`Taa = 20;`
115			`Toha = 5;`
116			`Tace = 20;`
117			`Tdoe = 9;`
118			`Tlzoe = 3;`
119			`Thzoe = 8;`
120			`Tlzce = 5; // not completely accurate. Tlzce2 = 3ns`
121			`Thzce = 8;`
122
123			`// write cycle`
124			`Twc = 20;`
125			`Tsce = 15;`
126			`Taw = 15;`
127			`Tpwe = 15;`
128			`Tsd = 10;`
129			`Thzwe = 7;`
130			`Tlzwe = 5;`
131			`end`
132
133			`//`
134			`// module body`
135			`//`
136
137			`// assign output`
138			`assign dataIO = (OE && !delayed_WE) ? data_temp : 8'bz;`
139
140			`// assign times`
141
142			`always@(posedge CE)`
143			`begin`
144			`CE_start <= $time;`
145
146			`#Tlzce OE_CE <= CE;`
147			`end`
148
149			`always@(negedge CE)`
150			`begin`
151			`CE_end <= $time;`
152
153			`#Thzce OE_CE <= CE;`
154			`end`
155
156			`always@(dataIO)`
157			`begin`
158			`dataIO_start <= $time;`
159			`end`
160
161			`always@(negedge WEn)`
162			`begin`
163			`write_WE_start <= $time;`
164
165			`# Thzwe delayed_WE <= !WEn;`
166			`end`
167
168			`always@(posedge WEn)`
169			`begin`
170			`read_WE_start <= $time;`
171
172			`#Tlzwe delayed_WE <= !WEn;`
173			`end`
174
175			`always@(Address)`
176			`begin`
177			`Address_start <= $time;`
178			`end`
179
180			`always@(negedge OEn)`
181			`begin`
182			`OEn_start <= $time;`
183
184			`#Tlzoe OE_OEn <= !OEn;`
185			`end`
186
187			`always@(posedge OEn)`
188			`begin`
189			`OEn_end <= $time;`
190
191			`#Thzoe OE_OEn <= !OEn;`
192			`end`
193			`//`
194			`// write cycles`
195			`//`
196
197			`always@(WEn or CE)`
198			`is_write <= !WEn && CE;`
199
200			`// write cycle no.1 & no.3 WE controlled`
201			`always@(posedge WEn or negedge CE)`
202			`begin`
203			`// check if CE asserted ( CE1n == 1'b0 && CE2 == 1'b1)`
204			`if (is_write)`
205			`begin`
206
207			`// check WE valid time`
208			`if ( ($time - write_WE_start) >= Tpwe)`
209			`begin`
210
211			`// check CE valid time`
212			`if ( ($time - CE_start) >= Tsce)`
213			`begin`
214
215			`// check data_in setup-time`
216			`if ( ($time - dataIO_start) >= Tsd)`
217			`begin`
218
219			`// check address valid time`
220			`if ( ($time - Address_start >= Taw) )`
221			`mem_array[Address] <= dataIO;`
222			`else`
223			`$display("Address setup to WE write end violation at time %t", $time);`
224			`end`
225			`else`
226			`$display("Data setup to WE write end violation at time %t", $time);`
227			`end`
228			`else`
229			`$display("CE to WE write end violation at time %t", $time);`
230			`end`
231			`else`
232			`$display("WE pulse width violation at time %t", $time);`
233			`end`
234			`end`
235
236
237			`//`
238			`// Read cycles`
239			`//`
240
241			`always@(Address or WEn or CE or OEn)`
242			`begin`
243			`// check if valid read cycle`
244			`if (CE && WEn)`
245			`begin`
246			`if ( (($time - CE_start) >= Trc) && (CE_start >= CE_end) &&`
247			`(($time - OEn_start) >= Trc) && (OEn_start >= OEn_end) ) // ???`
248			`begin`
249
250			`// check Trc`
251			`if ( ($time - Address_start < Trc) )`
252			`begin`
253			`$display("Read cycle time violation, caused by address change at time %t", $time);`
254			`$display("CE: %t, OEn: %t, Adr: %t", $time - CE_start, $time - OEn_start, $time - Address_start);`
255			`end`
256
257			`// read cycle no.1`
258			`read_cycle1 <= 1'b1;`
259			`read_cycle2 <= 1'b0;`
260			`end`
261			`else`
262			`begin`
263			`// read cycle no.2`
264			`read_cycle1 <= 1'b0;`
265			`read_cycle2 <= 1'b1;`
266			`end`
267			`end`
268			`else`
269			`begin`
270			`read_cycle1 = 1'b0;`
271			`read_cycle2 = 1'b0;`
272			`end`
273			`end`
274
275
276			`// perform actual read`
277			`always`
278			`begin`
279			`#1;`
280			`if (read_cycle1)`
281			`if ( ($time - Address_start) >= Taa)`
282			`data_temp <= mem_array[Address];`
283			`else if ( ($time - Address_start >= Toha) )`
284			`data_temp <= 8'bx;`
285
286			`if (read_cycle2)`
287			`if ( (($time - OEn_start) >= Tdoe) && (($time - CE_start) >= Tace) )`
288			`data_temp <= mem_array[Address];`
289			`else if ( (($time - OEn_start) >= Tlzoe) && (($time - CE_start) >= Tlzce) )`
290			`data_temp <= 8'bx;`
291			`end`
292
293			`endmodule`
294
295
296